| /kernel/linux/linux-4.19/Documentation/PCI/ |
| D | MSI-HOWTO.txt | 1 The MSI Driver Guide HOWTO
13 the advantages of using MSI over traditional interrupt mechanisms, how
14 to change your driver to use MSI or MSI-X and some basic diagnostics to
23 The MSI capability was first specified in PCI 2.2 and was later enhanced
24 in PCI 3.0 to allow each interrupt to be masked individually. The MSI-X
26 per device than MSI and allows interrupts to be independently configured.
28 Devices may support both MSI and MSI-X, but only one can be enabled at
35 traditional pin-based interrupts.
37 Pin-based PCI interrupts are often shared amongst several devices.
42 When a device writes data to memory, then raises a pin-based interrupt,
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| /kernel/linux/linux-5.10/drivers/pci/controller/ |
| D | pci-xgene-msi.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene MSI Driver
12 #include <linux/msi.h>
27 struct xgene_msi *msi; member
48 .name = "X-Gene1 MSI",
62 * X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where
63 * n is group number (0..F), x is index of registers in each group (0..7)
85 * Each index register supports 16 MSI vectors (0..15) to generate interrupt.
86 * There are total 16 GIC IRQs assigned for these 16 groups of MSI termination
89 * Each MSI termination group has 1 MSIINTn register (n is 0..15) to indicate
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| D | pcie-rcar-host.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
22 #include <linux/msi.h>
33 #include "pcie-rcar.h"
57 struct rcar_msi msi; member
74 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_config_access()
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| /kernel/linux/linux-5.10/arch/powerpc/platforms/4xx/ |
| D | msi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Adding PCI-E MSI support for PPC4XX SoCs.
12 #include <linux/msi.h>
19 #include <asm/ppc-pci.h>
21 #include <asm/dcr-regs.h>
51 err = msi_bitmap_alloc(&msi_data->bitmap, msi_irqs, in ppc4xx_msi_init_allocator()
52 dev->dev.of_node); in ppc4xx_msi_init_allocator()
56 err = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap); in ppc4xx_msi_init_allocator()
58 msi_bitmap_free(&msi_data->bitmap); in ppc4xx_msi_init_allocator()
67 int int_no = -ENOMEM; in ppc4xx_setup_msi_irqs()
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| /kernel/linux/linux-5.10/Documentation/PCI/ |
| D | msi-howto.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 The MSI Driver Guide HOWTO
16 the advantages of using MSI over traditional interrupt mechanisms, how
17 to change your driver to use MSI or MSI-X and some basic diagnostics to
27 The MSI capability was first specified in PCI 2.2 and was later enhanced
28 in PCI 3.0 to allow each interrupt to be masked individually. The MSI-X
30 per device than MSI and allows interrupts to be independently configured.
32 Devices may support both MSI and MSI-X, but only one can be enabled at
40 traditional pin-based interrupts.
42 Pin-based PCI interrupts are often shared amongst several devices.
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| /kernel/linux/linux-4.19/arch/powerpc/platforms/4xx/ |
| D | msi.c | 2 * Adding PCI-E MSI support for PPC4XX SoCs.
21 * MA 02111-1307 USA
26 #include <linux/msi.h>
33 #include <asm/ppc-pci.h>
35 #include <asm/dcr-regs.h>
65 err = msi_bitmap_alloc(&msi_data->bitmap, msi_irqs, in ppc4xx_msi_init_allocator()
66 dev->dev.of_node); in ppc4xx_msi_init_allocator()
70 err = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap); in ppc4xx_msi_init_allocator()
72 msi_bitmap_free(&msi_data->bitmap); in ppc4xx_msi_init_allocator()
81 int int_no = -ENOMEM; in ppc4xx_setup_msi_irqs()
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| /kernel/linux/linux-4.19/drivers/pci/controller/ |
| D | pci-xgene-msi.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene MSI Driver
12 #include <linux/msi.h>
27 struct xgene_msi *msi; member
48 .name = "X-Gene1 MSI",
62 * X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where
63 * n is group number (0..F), x is index of registers in each group (0..7)
85 * Each index register supports 16 MSI vectors (0..15) to generate interrupt.
86 * There are total 16 GIC IRQs assigned for these 16 groups of MSI termination
89 * Each MSI termination group has 1 MSIINTn register (n is 0..15) to indicate
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| D | pcie-rcar.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
22 #include <linux/msi.h>
62 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4)) argument
65 #define PCIELAR(x) (0x02200 + ((x) * 0x20)) argument
66 #define PCIELAMR(x) (0x02208 + ((x) * 0x20)) argument
72 #define PCIEPALR(x) (0x03400 + ((x) * 0x20)) argument
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| /kernel/linux/linux-4.19/arch/mips/pci/ |
| D | msi-xlp.c | 2 * Copyright (c) 2003-2012 Broadcom Corporation
39 #include <linux/msi.h>
50 #include <asm/netlogic/mips-extns.h>
52 #include <asm/netlogic/xlp-hal/iomap.h>
53 #include <asm/netlogic/xlp-hal/xlp.h>
54 #include <asm/netlogic/xlp-hal/pic.h>
55 #include <asm/netlogic/xlp-hal/pcibus.h>
56 #include <asm/netlogic/xlp-hal/bridge.h>
62 /* 128 MSI irqs per node, mapped starting at NLM_MSI_VEC_BASE */
68 /* get the link MSI vector from irq number */
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| D | msi-octeon.c | 6 * Copyright (C) 2005-2009, 2010 Cavium Networks
10 #include <linux/msi.h>
15 #include <asm/octeon/cvmx-npi-defs.h>
16 #include <asm/octeon/cvmx-pci-defs.h>
17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-sli-defs.h>
19 #include <asm/octeon/cvmx-pexp-defs.h>
20 #include <asm/octeon/pci-octeon.h>
23 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
31 * is used so we can disable all of the MSI interrupts when a device
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| /kernel/linux/linux-5.10/arch/mips/pci/ |
| D | msi-xlp.c | 2 * Copyright (c) 2003-2012 Broadcom Corporation
39 #include <linux/msi.h>
50 #include <asm/netlogic/mips-extns.h>
52 #include <asm/netlogic/xlp-hal/iomap.h>
53 #include <asm/netlogic/xlp-hal/xlp.h>
54 #include <asm/netlogic/xlp-hal/pic.h>
55 #include <asm/netlogic/xlp-hal/pcibus.h>
56 #include <asm/netlogic/xlp-hal/bridge.h>
62 /* 128 MSI irqs per node, mapped starting at NLM_MSI_VEC_BASE */
68 /* get the link MSI vector from irq number */
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| D | msi-octeon.c | 6 * Copyright (C) 2005-2009, 2010 Cavium Networks
10 #include <linux/msi.h>
15 #include <asm/octeon/cvmx-npi-defs.h>
16 #include <asm/octeon/cvmx-pci-defs.h>
17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-sli-defs.h>
19 #include <asm/octeon/cvmx-pexp-defs.h>
20 #include <asm/octeon/pci-octeon.h>
23 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
31 * is used so we can disable all of the MSI interrupts when a device
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| /kernel/linux/linux-4.19/drivers/pci/ |
| D | msi.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
18 #include <linux/msi.h>
39 domain = dev_get_msi_domain(&dev->dev); in pci_msi_setup_msi_irqs()
41 return msi_domain_alloc_irqs(domain, &dev->dev, nvec); in pci_msi_setup_msi_irqs()
50 domain = dev_get_msi_domain(&dev->dev); in pci_msi_teardown_msi_irqs()
52 msi_domain_free_irqs(domain, &dev->dev); in pci_msi_teardown_msi_irqs()
65 struct msi_controller *chip = dev->bus->msi; in arch_setup_msi_irq()
68 if (!chip || !chip->setup_irq) in arch_setup_msi_irq()
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| /kernel/linux/linux-4.19/include/linux/ |
| D | msi.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 u32 address_lo; /* low 32 bits of msi message address */
10 u32 address_hi; /* high 32 bits of msi message address */
11 u32 data; /* 16 bits of msi message data */
33 * platform_msi_desc - Platform device specific msi descriptor data
35 * @msi_index: The index of the MSI descriptor for multi MSI
43 * fsl_mc_msi_desc - FSL-MC device specific msi descriptor data
44 * @msi_index: The index of the MSI descriptor
51 * struct msi_desc - Descriptor structure for MSI based interrupts
56 * @msg: The last set MSI message cached for reuse
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| /kernel/linux/linux-5.10/include/linux/ |
| D | msi.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 u32 address_lo; /* low 32 bits of msi message address */
10 u32 address_hi; /* high 32 bits of msi message address */
11 u32 data; /* 16 bits of msi message data */
33 * platform_msi_desc - Platform device specific msi descriptor data
35 * @msi_index: The index of the MSI descriptor for multi MSI
43 * fsl_mc_msi_desc - FSL-MC device specific msi descriptor data
44 * @msi_index: The index of the MSI descriptor
51 * ti_sci_inta_msi_desc - TISCI based INTA specific msi descriptor data
59 * struct msi_desc - Descriptor structure for MSI based interrupts
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| /kernel/linux/linux-5.10/drivers/pci/ |
| D | msi.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
18 #include <linux/msi.h>
39 domain = dev_get_msi_domain(&dev->dev); in pci_msi_setup_msi_irqs()
41 return msi_domain_alloc_irqs(domain, &dev->dev, nvec); in pci_msi_setup_msi_irqs()
50 domain = dev_get_msi_domain(&dev->dev); in pci_msi_teardown_msi_irqs()
52 msi_domain_free_irqs(domain, &dev->dev); in pci_msi_teardown_msi_irqs()
65 struct msi_controller *chip = dev->bus->msi; in arch_setup_msi_irq()
68 if (!chip || !chip->setup_irq) in arch_setup_msi_irq()
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| /kernel/linux/linux-4.19/arch/sparc/kernel/ |
| D | pci_msi.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_msi.c: Sparc64 MSI support common layer.
16 struct pci_pbm_info *pbm = msiq_cookie->pbm; in sparc64_msiq_interrupt()
17 unsigned long msiqid = msiq_cookie->msiqid; in sparc64_msiq_interrupt()
22 ops = pbm->msi_ops; in sparc64_msiq_interrupt()
24 err = ops->get_head(pbm, msiqid, &head); in sparc64_msiq_interrupt()
30 unsigned long msi; in sparc64_msiq_interrupt() local
32 err = ops->dequeue_msi(pbm, msiqid, &head, &msi); in sparc64_msiq_interrupt()
36 irq = pbm->msi_irq_table[msi - pbm->msi_first]; in sparc64_msiq_interrupt()
47 err = ops->set_head(pbm, msiqid, head); in sparc64_msiq_interrupt()
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| /kernel/linux/linux-5.10/arch/sparc/kernel/ |
| D | pci_msi.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_msi.c: Sparc64 MSI support common layer.
16 struct pci_pbm_info *pbm = msiq_cookie->pbm; in sparc64_msiq_interrupt()
17 unsigned long msiqid = msiq_cookie->msiqid; in sparc64_msiq_interrupt()
22 ops = pbm->msi_ops; in sparc64_msiq_interrupt()
24 err = ops->get_head(pbm, msiqid, &head); in sparc64_msiq_interrupt()
30 unsigned long msi; in sparc64_msiq_interrupt() local
32 err = ops->dequeue_msi(pbm, msiqid, &head, &msi); in sparc64_msiq_interrupt()
36 irq = pbm->msi_irq_table[msi - pbm->msi_first]; in sparc64_msiq_interrupt()
47 err = ops->set_head(pbm, msiqid, head); in sparc64_msiq_interrupt()
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| /kernel/linux/linux-5.10/arch/powerpc/platforms/cell/ |
| D | axon_msi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/msi.h>
51 * To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
52 * 8-9 of the MSIC control reg.
54 #define MSIC_CTRL_FIFO_SIZE (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)
58 * the bounds of the FIFO. Also they should always be 16-byte aligned.
60 #define MSIC_FIFO_SIZE_MASK ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)
87 pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n); in msic_dcr_write()
89 dcr_write(msic->dcr_host, dcr_n, val); in msic_dcr_write()
96 u32 write_offset, msi; in axon_msi_cascade() local
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| /kernel/linux/linux-4.19/arch/powerpc/platforms/cell/ |
| D | axon_msi.c | 15 #include <linux/msi.h>
55 * To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
56 * 8-9 of the MSIC control reg.
58 #define MSIC_CTRL_FIFO_SIZE (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)
62 * the bounds of the FIFO. Also they should always be 16-byte aligned.
64 #define MSIC_FIFO_SIZE_MASK ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)
91 pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n); in msic_dcr_write()
93 dcr_write(msic->dcr_host, dcr_n, val); in msic_dcr_write()
100 u32 write_offset, msi; in axon_msi_cascade() local
104 write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG); in axon_msi_cascade()
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/pci/ |
| D | xgene-pci-msi.txt | 1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
8 - reg: physical base address (0x79000000) and length (0x900000) for controller
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
11 - reg-names: not required
12 - interrupts: A list of 16 interrupt outputs of the controller, starting from
14 - interrupt-names: not required
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | xgene-pci-msi.txt | 1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
8 - reg: physical base address (0x79000000) and length (0x900000) for controller
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
11 - reg-names: not required
12 - interrupts: A list of 16 interrupt outputs of the controller, starting from
14 - interrupt-names: not required
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| /kernel/linux/linux-4.19/drivers/xen/xen-pciback/ |
| D | pciback_ops.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Backend Operations - respond to PCI requests from Frontend
37 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) in xen_pcibk_control_isr()
41 dev_data->enable_intx = 0; in xen_pcibk_control_isr()
42 dev_data->ack_intr = 0; in xen_pcibk_control_isr()
44 enable = dev_data->enable_intx; in xen_pcibk_control_isr()
47 if (!enable && !dev_data->isr_on) in xen_pcibk_control_isr()
51 * b/c when device transitions to MSI, the dev->irq is in xen_pcibk_control_isr()
52 * overwritten with the MSI vector. in xen_pcibk_control_isr()
55 dev_data->irq = dev->irq; in xen_pcibk_control_isr()
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| /kernel/linux/linux-5.10/drivers/pci/controller/mobiveil/ |
| D | pcie-mobiveil-host.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright 2019-2020 NXP
19 #include <linux/msi.h>
28 #include "pcie-mobiveil.h"
40 if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0)) in mobiveil_pcie_valid_device()
47 * mobiveil_pcie_map_bus - routine to get the configuration base of either
53 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus()
54 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
62 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
70 value = bus->number << PAB_BUS_SHIFT | in mobiveil_pcie_map_bus()
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| /kernel/linux/linux-5.10/arch/powerpc/sysdev/ |
| D | mpic_u3msi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
8 #include <linux/msi.h>
12 #include <asm/ppc-pci.h>
39 .name = "MPIC-U3MSI",
66 for (bus = pdev->bus; bus && bus->self; bus = bus->parent) { in find_ht_magic_addr()
67 pos = pci_find_ht_capability(bus->self, HT_CAPTYPE_MSI_MAPPING); in find_ht_magic_addr()
69 return read_ht_magic_addr(bus->self, pos); in find_ht_magic_addr()
77 struct pci_controller *hose = pci_bus_to_host(pdev->bus); in find_u4_magic_addr()
82 * the MSI number and that triggers the right interrupt, but in find_u4_magic_addr()
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