1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014 Renesas Electronics Europe Ltd
5 *
6 * Based on:
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
10 *
11 * Author: Phil Edworthy <phil.edworthy@renesas.com>
12 */
13
14 #include <linux/bitops.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/msi.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/phy/phy.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/slab.h>
32
33 #include "../pci.h"
34
35 #define PCIECAR 0x000010
36 #define PCIECCTLR 0x000018
37 #define CONFIG_SEND_ENABLE BIT(31)
38 #define TYPE0 (0 << 8)
39 #define TYPE1 BIT(8)
40 #define PCIECDR 0x000020
41 #define PCIEMSR 0x000028
42 #define PCIEINTXR 0x000400
43 #define PCIEPHYSR 0x0007f0
44 #define PHYRDY BIT(0)
45 #define PCIEMSITXR 0x000840
46
47 /* Transfer control */
48 #define PCIETCTLR 0x02000
49 #define DL_DOWN BIT(3)
50 #define CFINIT 1
51 #define PCIETSTR 0x02004
52 #define DATA_LINK_ACTIVE 1
53 #define PCIEERRFR 0x02020
54 #define UNSUPPORTED_REQUEST BIT(4)
55 #define PCIEMSIFR 0x02044
56 #define PCIEMSIALR 0x02048
57 #define MSIFE 1
58 #define PCIEMSIAUR 0x0204c
59 #define PCIEMSIIER 0x02050
60
61 /* root port address */
62 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
63
64 /* local address reg & mask */
65 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
66 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
67 #define LAM_PREFETCH BIT(3)
68 #define LAM_64BIT BIT(2)
69 #define LAR_ENABLE BIT(1)
70
71 /* PCIe address reg & mask */
72 #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
73 #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
74 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
75 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
76 #define PAR_ENABLE BIT(31)
77 #define IO_SPACE BIT(8)
78
79 /* Configuration */
80 #define PCICONF(x) (0x010000 + ((x) * 0x4))
81 #define PMCAP(x) (0x010040 + ((x) * 0x4))
82 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
83 #define VCCAP(x) (0x010100 + ((x) * 0x4))
84
85 /* link layer */
86 #define IDSETR1 0x011004
87 #define TLCTLR 0x011048
88 #define MACSR 0x011054
89 #define SPCHGFIN BIT(4)
90 #define SPCHGFAIL BIT(6)
91 #define SPCHGSUC BIT(7)
92 #define LINK_SPEED (0xf << 16)
93 #define LINK_SPEED_2_5GTS (1 << 16)
94 #define LINK_SPEED_5_0GTS (2 << 16)
95 #define MACCTLR 0x011058
96 #define MACCTLR_NFTS_MASK GENMASK(23, 16) /* The name is from SH7786 */
97 #define SPEED_CHANGE BIT(24)
98 #define SCRAMBLE_DISABLE BIT(27)
99 #define LTSMDIS BIT(31)
100 #define MACCTLR_INIT_VAL (LTSMDIS | MACCTLR_NFTS_MASK)
101 #define PMSR 0x01105c
102 #define MACS2R 0x011078
103 #define MACCGSPSETR 0x011084
104 #define SPCNGRSN BIT(31)
105
106 /* R-Car H1 PHY */
107 #define H1_PCIEPHYADRR 0x04000c
108 #define WRITE_CMD BIT(16)
109 #define PHY_ACK BIT(24)
110 #define RATE_POS 12
111 #define LANE_POS 8
112 #define ADR_POS 0
113 #define H1_PCIEPHYDOUTR 0x040014
114
115 /* R-Car Gen2 PHY */
116 #define GEN2_PCIEPHYADDR 0x780
117 #define GEN2_PCIEPHYDATA 0x784
118 #define GEN2_PCIEPHYCTRL 0x78c
119
120 #define INT_PCI_MSI_NR 32
121
122 #define RCONF(x) (PCICONF(0) + (x))
123 #define RPMCAP(x) (PMCAP(0) + (x))
124 #define REXPCAP(x) (EXPCAP(0) + (x))
125 #define RVCCAP(x) (VCCAP(0) + (x))
126
127 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
128 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
129 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
130
131 #define RCAR_PCI_MAX_RESOURCES 4
132 #define MAX_NR_INBOUND_MAPS 6
133
134 struct rcar_msi {
135 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
136 struct irq_domain *domain;
137 struct msi_controller chip;
138 unsigned long pages;
139 struct mutex lock;
140 int irq1;
141 int irq2;
142 };
143
to_rcar_msi(struct msi_controller * chip)144 static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
145 {
146 return container_of(chip, struct rcar_msi, chip);
147 }
148
149 /* Structure representing the PCIe interface */
150 struct rcar_pcie {
151 struct device *dev;
152 struct phy *phy;
153 void __iomem *base;
154 struct list_head resources;
155 int root_bus_nr;
156 struct clk *bus_clk;
157 struct rcar_msi msi;
158 };
159
rcar_pci_write_reg(struct rcar_pcie * pcie,unsigned long val,unsigned long reg)160 static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
161 unsigned long reg)
162 {
163 writel(val, pcie->base + reg);
164 }
165
rcar_pci_read_reg(struct rcar_pcie * pcie,unsigned long reg)166 static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie,
167 unsigned long reg)
168 {
169 return readl(pcie->base + reg);
170 }
171
172 enum {
173 RCAR_PCI_ACCESS_READ,
174 RCAR_PCI_ACCESS_WRITE,
175 };
176
rcar_rmw32(struct rcar_pcie * pcie,int where,u32 mask,u32 data)177 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
178 {
179 int shift = 8 * (where & 3);
180 u32 val = rcar_pci_read_reg(pcie, where & ~3);
181
182 val &= ~(mask << shift);
183 val |= data << shift;
184 rcar_pci_write_reg(pcie, val, where & ~3);
185 }
186
rcar_read_conf(struct rcar_pcie * pcie,int where)187 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
188 {
189 int shift = 8 * (where & 3);
190 u32 val = rcar_pci_read_reg(pcie, where & ~3);
191
192 return val >> shift;
193 }
194
195 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
rcar_pcie_config_access(struct rcar_pcie * pcie,unsigned char access_type,struct pci_bus * bus,unsigned int devfn,int where,u32 * data)196 static int rcar_pcie_config_access(struct rcar_pcie *pcie,
197 unsigned char access_type, struct pci_bus *bus,
198 unsigned int devfn, int where, u32 *data)
199 {
200 int dev, func, reg, index;
201
202 dev = PCI_SLOT(devfn);
203 func = PCI_FUNC(devfn);
204 reg = where & ~3;
205 index = reg / 4;
206
207 /*
208 * While each channel has its own memory-mapped extended config
209 * space, it's generally only accessible when in endpoint mode.
210 * When in root complex mode, the controller is unable to target
211 * itself with either type 0 or type 1 accesses, and indeed, any
212 * controller initiated target transfer to its own config space
213 * result in a completer abort.
214 *
215 * Each channel effectively only supports a single device, but as
216 * the same channel <-> device access works for any PCI_SLOT()
217 * value, we cheat a bit here and bind the controller's config
218 * space to devfn 0 in order to enable self-enumeration. In this
219 * case the regular ECAR/ECDR path is sidelined and the mangled
220 * config access itself is initiated as an internal bus transaction.
221 */
222 if (pci_is_root_bus(bus)) {
223 if (dev != 0)
224 return PCIBIOS_DEVICE_NOT_FOUND;
225
226 if (access_type == RCAR_PCI_ACCESS_READ) {
227 *data = rcar_pci_read_reg(pcie, PCICONF(index));
228 } else {
229 /* Keep an eye out for changes to the root bus number */
230 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
231 pcie->root_bus_nr = *data & 0xff;
232
233 rcar_pci_write_reg(pcie, *data, PCICONF(index));
234 }
235
236 return PCIBIOS_SUCCESSFUL;
237 }
238
239 if (pcie->root_bus_nr < 0)
240 return PCIBIOS_DEVICE_NOT_FOUND;
241
242 /* Clear errors */
243 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
244
245 /* Set the PIO address */
246 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
247 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
248
249 /* Enable the configuration access */
250 if (bus->parent->number == pcie->root_bus_nr)
251 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
252 else
253 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
254
255 /* Check for errors */
256 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
257 return PCIBIOS_DEVICE_NOT_FOUND;
258
259 /* Check for master and target aborts */
260 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
261 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
262 return PCIBIOS_DEVICE_NOT_FOUND;
263
264 if (access_type == RCAR_PCI_ACCESS_READ)
265 *data = rcar_pci_read_reg(pcie, PCIECDR);
266 else
267 rcar_pci_write_reg(pcie, *data, PCIECDR);
268
269 /* Disable the configuration access */
270 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
271
272 return PCIBIOS_SUCCESSFUL;
273 }
274
rcar_pcie_read_conf(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)275 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
276 int where, int size, u32 *val)
277 {
278 struct rcar_pcie *pcie = bus->sysdata;
279 int ret;
280
281 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
282 bus, devfn, where, val);
283 if (ret != PCIBIOS_SUCCESSFUL) {
284 *val = 0xffffffff;
285 return ret;
286 }
287
288 if (size == 1)
289 *val = (*val >> (8 * (where & 3))) & 0xff;
290 else if (size == 2)
291 *val = (*val >> (8 * (where & 2))) & 0xffff;
292
293 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
294 bus->number, devfn, where, size, (unsigned long)*val);
295
296 return ret;
297 }
298
299 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
rcar_pcie_write_conf(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 val)300 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
301 int where, int size, u32 val)
302 {
303 struct rcar_pcie *pcie = bus->sysdata;
304 int shift, ret;
305 u32 data;
306
307 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
308 bus, devfn, where, &data);
309 if (ret != PCIBIOS_SUCCESSFUL)
310 return ret;
311
312 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
313 bus->number, devfn, where, size, (unsigned long)val);
314
315 if (size == 1) {
316 shift = 8 * (where & 3);
317 data &= ~(0xff << shift);
318 data |= ((val & 0xff) << shift);
319 } else if (size == 2) {
320 shift = 8 * (where & 2);
321 data &= ~(0xffff << shift);
322 data |= ((val & 0xffff) << shift);
323 } else
324 data = val;
325
326 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE,
327 bus, devfn, where, &data);
328
329 return ret;
330 }
331
332 static struct pci_ops rcar_pcie_ops = {
333 .read = rcar_pcie_read_conf,
334 .write = rcar_pcie_write_conf,
335 };
336
rcar_pcie_setup_window(int win,struct rcar_pcie * pcie,struct resource_entry * window)337 static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie,
338 struct resource_entry *window)
339 {
340 /* Setup PCIe address space mappings for each resource */
341 resource_size_t size;
342 resource_size_t res_start;
343 struct resource *res = window->res;
344 u32 mask;
345
346 rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
347
348 /*
349 * The PAMR mask is calculated in units of 128Bytes, which
350 * keeps things pretty simple.
351 */
352 size = resource_size(res);
353 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
354 rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
355
356 if (res->flags & IORESOURCE_IO)
357 res_start = pci_pio_to_address(res->start) - window->offset;
358 else
359 res_start = res->start - window->offset;
360
361 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
362 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
363 PCIEPALR(win));
364
365 /* First resource is for IO */
366 mask = PAR_ENABLE;
367 if (res->flags & IORESOURCE_IO)
368 mask |= IO_SPACE;
369
370 rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
371 }
372
rcar_pcie_setup(struct list_head * resource,struct rcar_pcie * pci)373 static int rcar_pcie_setup(struct list_head *resource, struct rcar_pcie *pci)
374 {
375 struct resource_entry *win;
376 int i = 0;
377
378 /* Setup PCI resources */
379 resource_list_for_each_entry(win, &pci->resources) {
380 struct resource *res = win->res;
381
382 if (!res->flags)
383 continue;
384
385 switch (resource_type(res)) {
386 case IORESOURCE_IO:
387 case IORESOURCE_MEM:
388 rcar_pcie_setup_window(i, pci, win);
389 i++;
390 break;
391 case IORESOURCE_BUS:
392 pci->root_bus_nr = res->start;
393 break;
394 default:
395 continue;
396 }
397
398 pci_add_resource(resource, res);
399 }
400
401 return 1;
402 }
403
rcar_pcie_force_speedup(struct rcar_pcie * pcie)404 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie)
405 {
406 struct device *dev = pcie->dev;
407 unsigned int timeout = 1000;
408 u32 macsr;
409
410 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS)
411 return;
412
413 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) {
414 dev_err(dev, "Speed change already in progress\n");
415 return;
416 }
417
418 macsr = rcar_pci_read_reg(pcie, MACSR);
419 if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS)
420 goto done;
421
422 /* Set target link speed to 5.0 GT/s */
423 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS,
424 PCI_EXP_LNKSTA_CLS_5_0GB);
425
426 /* Set speed change reason as intentional factor */
427 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0);
428
429 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */
430 if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL))
431 rcar_pci_write_reg(pcie, macsr, MACSR);
432
433 /* Start link speed change */
434 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE);
435
436 while (timeout--) {
437 macsr = rcar_pci_read_reg(pcie, MACSR);
438 if (macsr & SPCHGFIN) {
439 /* Clear the interrupt bits */
440 rcar_pci_write_reg(pcie, macsr, MACSR);
441
442 if (macsr & SPCHGFAIL)
443 dev_err(dev, "Speed change failed\n");
444
445 goto done;
446 }
447
448 msleep(1);
449 }
450
451 dev_err(dev, "Speed change timed out\n");
452
453 done:
454 dev_info(dev, "Current link speed is %s GT/s\n",
455 (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5");
456 }
457
rcar_pcie_enable(struct rcar_pcie * pcie)458 static int rcar_pcie_enable(struct rcar_pcie *pcie)
459 {
460 struct device *dev = pcie->dev;
461 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
462 struct pci_bus *bus, *child;
463 int ret;
464
465 /* Try setting 5 GT/s link speed */
466 rcar_pcie_force_speedup(pcie);
467
468 rcar_pcie_setup(&bridge->windows, pcie);
469
470 pci_add_flags(PCI_REASSIGN_ALL_BUS);
471
472 bridge->dev.parent = dev;
473 bridge->sysdata = pcie;
474 bridge->busnr = pcie->root_bus_nr;
475 bridge->ops = &rcar_pcie_ops;
476 bridge->map_irq = of_irq_parse_and_map_pci;
477 bridge->swizzle_irq = pci_common_swizzle;
478 if (IS_ENABLED(CONFIG_PCI_MSI))
479 bridge->msi = &pcie->msi.chip;
480
481 ret = pci_scan_root_bus_bridge(bridge);
482 if (ret < 0)
483 return ret;
484
485 bus = bridge->bus;
486
487 pci_bus_size_bridges(bus);
488 pci_bus_assign_resources(bus);
489
490 list_for_each_entry(child, &bus->children, node)
491 pcie_bus_configure_settings(child);
492
493 pci_bus_add_devices(bus);
494
495 return 0;
496 }
497
phy_wait_for_ack(struct rcar_pcie * pcie)498 static int phy_wait_for_ack(struct rcar_pcie *pcie)
499 {
500 struct device *dev = pcie->dev;
501 unsigned int timeout = 100;
502
503 while (timeout--) {
504 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
505 return 0;
506
507 udelay(100);
508 }
509
510 dev_err(dev, "Access to PCIe phy timed out\n");
511
512 return -ETIMEDOUT;
513 }
514
phy_write_reg(struct rcar_pcie * pcie,unsigned int rate,unsigned int addr,unsigned int lane,unsigned int data)515 static void phy_write_reg(struct rcar_pcie *pcie,
516 unsigned int rate, unsigned int addr,
517 unsigned int lane, unsigned int data)
518 {
519 unsigned long phyaddr;
520
521 phyaddr = WRITE_CMD |
522 ((rate & 1) << RATE_POS) |
523 ((lane & 0xf) << LANE_POS) |
524 ((addr & 0xff) << ADR_POS);
525
526 /* Set write data */
527 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
528 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
529
530 /* Ignore errors as they will be dealt with if the data link is down */
531 phy_wait_for_ack(pcie);
532
533 /* Clear command */
534 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
535 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
536
537 /* Ignore errors as they will be dealt with if the data link is down */
538 phy_wait_for_ack(pcie);
539 }
540
rcar_pcie_wait_for_phyrdy(struct rcar_pcie * pcie)541 static int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie)
542 {
543 unsigned int timeout = 10;
544
545 while (timeout--) {
546 if (rcar_pci_read_reg(pcie, PCIEPHYSR) & PHYRDY)
547 return 0;
548
549 msleep(5);
550 }
551
552 return -ETIMEDOUT;
553 }
554
rcar_pcie_wait_for_dl(struct rcar_pcie * pcie)555 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
556 {
557 unsigned int timeout = 10000;
558
559 while (timeout--) {
560 if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
561 return 0;
562
563 udelay(5);
564 cpu_relax();
565 }
566
567 return -ETIMEDOUT;
568 }
569
rcar_pcie_hw_init(struct rcar_pcie * pcie)570 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
571 {
572 int err;
573
574 /* Begin initialization */
575 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
576
577 /* Set mode */
578 rcar_pci_write_reg(pcie, 1, PCIEMSR);
579
580 err = rcar_pcie_wait_for_phyrdy(pcie);
581 if (err)
582 return err;
583
584 /*
585 * Initial header for port config space is type 1, set the device
586 * class to match. Hardware takes care of propagating the IDSETR
587 * settings, so there is no need to bother with a quirk.
588 */
589 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
590
591 /*
592 * Setup Secondary Bus Number & Subordinate Bus Number, even though
593 * they aren't used, to avoid bridge being detected as broken.
594 */
595 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
596 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
597
598 /* Initialize default capabilities. */
599 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
600 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
601 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
602 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
603 PCI_HEADER_TYPE_BRIDGE);
604
605 /* Enable data link layer active state reporting */
606 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
607 PCI_EXP_LNKCAP_DLLLARC);
608
609 /* Write out the physical slot number = 0 */
610 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
611
612 /* Set the completion timer timeout to the maximum 50ms. */
613 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
614
615 /* Terminate list of capabilities (Next Capability Offset=0) */
616 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
617
618 /* Enable MSI */
619 if (IS_ENABLED(CONFIG_PCI_MSI))
620 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
621
622 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
623
624 /* Finish initialization - establish a PCI Express link */
625 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
626
627 /* This will timeout if we don't have a link. */
628 err = rcar_pcie_wait_for_dl(pcie);
629 if (err)
630 return err;
631
632 /* Enable INTx interrupts */
633 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
634
635 wmb();
636
637 return 0;
638 }
639
rcar_pcie_phy_init_h1(struct rcar_pcie * pcie)640 static int rcar_pcie_phy_init_h1(struct rcar_pcie *pcie)
641 {
642 /* Initialize the phy */
643 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
644 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
645 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
646 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
647 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
648 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
649 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
650 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
651 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
652 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
653 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
654 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
655
656 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
657 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
658 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
659
660 return 0;
661 }
662
rcar_pcie_phy_init_gen2(struct rcar_pcie * pcie)663 static int rcar_pcie_phy_init_gen2(struct rcar_pcie *pcie)
664 {
665 /*
666 * These settings come from the R-Car Series, 2nd Generation User's
667 * Manual, section 50.3.1 (2) Initialization of the physical layer.
668 */
669 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
670 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
671 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
672 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
673
674 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
675 /* The following value is for DC connection, no termination resistor */
676 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
677 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
678 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
679
680 return 0;
681 }
682
rcar_pcie_phy_init_gen3(struct rcar_pcie * pcie)683 static int rcar_pcie_phy_init_gen3(struct rcar_pcie *pcie)
684 {
685 int err;
686
687 err = phy_init(pcie->phy);
688 if (err)
689 return err;
690
691 err = phy_power_on(pcie->phy);
692 if (err)
693 phy_exit(pcie->phy);
694
695 return err;
696 }
697
rcar_msi_alloc(struct rcar_msi * chip)698 static int rcar_msi_alloc(struct rcar_msi *chip)
699 {
700 int msi;
701
702 mutex_lock(&chip->lock);
703
704 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
705 if (msi < INT_PCI_MSI_NR)
706 set_bit(msi, chip->used);
707 else
708 msi = -ENOSPC;
709
710 mutex_unlock(&chip->lock);
711
712 return msi;
713 }
714
rcar_msi_alloc_region(struct rcar_msi * chip,int no_irqs)715 static int rcar_msi_alloc_region(struct rcar_msi *chip, int no_irqs)
716 {
717 int msi;
718
719 mutex_lock(&chip->lock);
720 msi = bitmap_find_free_region(chip->used, INT_PCI_MSI_NR,
721 order_base_2(no_irqs));
722 mutex_unlock(&chip->lock);
723
724 return msi;
725 }
726
rcar_msi_free(struct rcar_msi * chip,unsigned long irq)727 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
728 {
729 mutex_lock(&chip->lock);
730 clear_bit(irq, chip->used);
731 mutex_unlock(&chip->lock);
732 }
733
rcar_pcie_msi_irq(int irq,void * data)734 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
735 {
736 struct rcar_pcie *pcie = data;
737 struct rcar_msi *msi = &pcie->msi;
738 struct device *dev = pcie->dev;
739 unsigned long reg;
740
741 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
742
743 /* MSI & INTx share an interrupt - we only handle MSI here */
744 if (!reg)
745 return IRQ_NONE;
746
747 while (reg) {
748 unsigned int index = find_first_bit(®, 32);
749 unsigned int irq;
750
751 /* clear the interrupt */
752 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
753
754 irq = irq_find_mapping(msi->domain, index);
755 if (irq) {
756 if (test_bit(index, msi->used))
757 generic_handle_irq(irq);
758 else
759 dev_info(dev, "unhandled MSI\n");
760 } else {
761 /* Unknown MSI, just clear it */
762 dev_dbg(dev, "unexpected MSI\n");
763 }
764
765 /* see if there's any more pending in this vector */
766 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
767 }
768
769 return IRQ_HANDLED;
770 }
771
rcar_msi_setup_irq(struct msi_controller * chip,struct pci_dev * pdev,struct msi_desc * desc)772 static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
773 struct msi_desc *desc)
774 {
775 struct rcar_msi *msi = to_rcar_msi(chip);
776 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
777 struct msi_msg msg;
778 unsigned int irq;
779 int hwirq;
780
781 hwirq = rcar_msi_alloc(msi);
782 if (hwirq < 0)
783 return hwirq;
784
785 irq = irq_find_mapping(msi->domain, hwirq);
786 if (!irq) {
787 rcar_msi_free(msi, hwirq);
788 return -EINVAL;
789 }
790
791 irq_set_msi_desc(irq, desc);
792
793 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
794 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
795 msg.data = hwirq;
796
797 pci_write_msi_msg(irq, &msg);
798
799 return 0;
800 }
801
rcar_msi_setup_irqs(struct msi_controller * chip,struct pci_dev * pdev,int nvec,int type)802 static int rcar_msi_setup_irqs(struct msi_controller *chip,
803 struct pci_dev *pdev, int nvec, int type)
804 {
805 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
806 struct rcar_msi *msi = to_rcar_msi(chip);
807 struct msi_desc *desc;
808 struct msi_msg msg;
809 unsigned int irq;
810 int hwirq;
811 int i;
812
813 /* MSI-X interrupts are not supported */
814 if (type == PCI_CAP_ID_MSIX)
815 return -EINVAL;
816
817 WARN_ON(!list_is_singular(&pdev->dev.msi_list));
818 desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
819
820 hwirq = rcar_msi_alloc_region(msi, nvec);
821 if (hwirq < 0)
822 return -ENOSPC;
823
824 irq = irq_find_mapping(msi->domain, hwirq);
825 if (!irq)
826 return -ENOSPC;
827
828 for (i = 0; i < nvec; i++) {
829 /*
830 * irq_create_mapping() called from rcar_pcie_probe() pre-
831 * allocates descs, so there is no need to allocate descs here.
832 * We can therefore assume that if irq_find_mapping() above
833 * returns non-zero, then the descs are also successfully
834 * allocated.
835 */
836 if (irq_set_msi_desc_off(irq, i, desc)) {
837 /* TODO: clear */
838 return -EINVAL;
839 }
840 }
841
842 desc->nvec_used = nvec;
843 desc->msi_attrib.multiple = order_base_2(nvec);
844
845 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
846 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
847 msg.data = hwirq;
848
849 pci_write_msi_msg(irq, &msg);
850
851 return 0;
852 }
853
rcar_msi_teardown_irq(struct msi_controller * chip,unsigned int irq)854 static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
855 {
856 struct rcar_msi *msi = to_rcar_msi(chip);
857 struct irq_data *d = irq_get_irq_data(irq);
858
859 rcar_msi_free(msi, d->hwirq);
860 }
861
862 static struct irq_chip rcar_msi_irq_chip = {
863 .name = "R-Car PCIe MSI",
864 .irq_enable = pci_msi_unmask_irq,
865 .irq_disable = pci_msi_mask_irq,
866 .irq_mask = pci_msi_mask_irq,
867 .irq_unmask = pci_msi_unmask_irq,
868 };
869
rcar_msi_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)870 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
871 irq_hw_number_t hwirq)
872 {
873 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
874 irq_set_chip_data(irq, domain->host_data);
875
876 return 0;
877 }
878
879 static const struct irq_domain_ops msi_domain_ops = {
880 .map = rcar_msi_map,
881 };
882
rcar_pcie_unmap_msi(struct rcar_pcie * pcie)883 static void rcar_pcie_unmap_msi(struct rcar_pcie *pcie)
884 {
885 struct rcar_msi *msi = &pcie->msi;
886 int i, irq;
887
888 for (i = 0; i < INT_PCI_MSI_NR; i++) {
889 irq = irq_find_mapping(msi->domain, i);
890 if (irq > 0)
891 irq_dispose_mapping(irq);
892 }
893
894 irq_domain_remove(msi->domain);
895 }
896
rcar_pcie_enable_msi(struct rcar_pcie * pcie)897 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
898 {
899 struct device *dev = pcie->dev;
900 struct rcar_msi *msi = &pcie->msi;
901 phys_addr_t base;
902 int err, i;
903
904 mutex_init(&msi->lock);
905
906 msi->chip.dev = dev;
907 msi->chip.setup_irq = rcar_msi_setup_irq;
908 msi->chip.setup_irqs = rcar_msi_setup_irqs;
909 msi->chip.teardown_irq = rcar_msi_teardown_irq;
910
911 msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR,
912 &msi_domain_ops, &msi->chip);
913 if (!msi->domain) {
914 dev_err(dev, "failed to create IRQ domain\n");
915 return -ENOMEM;
916 }
917
918 for (i = 0; i < INT_PCI_MSI_NR; i++)
919 irq_create_mapping(msi->domain, i);
920
921 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
922 err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq,
923 IRQF_SHARED | IRQF_NO_THREAD,
924 rcar_msi_irq_chip.name, pcie);
925 if (err < 0) {
926 dev_err(dev, "failed to request IRQ: %d\n", err);
927 goto err;
928 }
929
930 err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq,
931 IRQF_SHARED | IRQF_NO_THREAD,
932 rcar_msi_irq_chip.name, pcie);
933 if (err < 0) {
934 dev_err(dev, "failed to request IRQ: %d\n", err);
935 goto err;
936 }
937
938 /* setup MSI data target */
939 msi->pages = __get_free_pages(GFP_KERNEL, 0);
940 if (!msi->pages) {
941 err = -ENOMEM;
942 goto err;
943 }
944 base = virt_to_phys((void *)msi->pages);
945
946 rcar_pci_write_reg(pcie, lower_32_bits(base) | MSIFE, PCIEMSIALR);
947 rcar_pci_write_reg(pcie, upper_32_bits(base), PCIEMSIAUR);
948
949 /* enable all MSI interrupts */
950 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
951
952 return 0;
953
954 err:
955 rcar_pcie_unmap_msi(pcie);
956 return err;
957 }
958
rcar_pcie_teardown_msi(struct rcar_pcie * pcie)959 static void rcar_pcie_teardown_msi(struct rcar_pcie *pcie)
960 {
961 struct rcar_msi *msi = &pcie->msi;
962
963 /* Disable all MSI interrupts */
964 rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
965
966 /* Disable address decoding of the MSI interrupt, MSIFE */
967 rcar_pci_write_reg(pcie, 0, PCIEMSIALR);
968
969 free_pages(msi->pages, 0);
970
971 rcar_pcie_unmap_msi(pcie);
972 }
973
rcar_pcie_get_resources(struct rcar_pcie * pcie)974 static int rcar_pcie_get_resources(struct rcar_pcie *pcie)
975 {
976 struct device *dev = pcie->dev;
977 struct resource res;
978 int err, i;
979
980 pcie->phy = devm_phy_optional_get(dev, "pcie");
981 if (IS_ERR(pcie->phy))
982 return PTR_ERR(pcie->phy);
983
984 err = of_address_to_resource(dev->of_node, 0, &res);
985 if (err)
986 return err;
987
988 pcie->base = devm_ioremap_resource(dev, &res);
989 if (IS_ERR(pcie->base))
990 return PTR_ERR(pcie->base);
991
992 pcie->bus_clk = devm_clk_get(dev, "pcie_bus");
993 if (IS_ERR(pcie->bus_clk)) {
994 dev_err(dev, "cannot get pcie bus clock\n");
995 return PTR_ERR(pcie->bus_clk);
996 }
997
998 i = irq_of_parse_and_map(dev->of_node, 0);
999 if (!i) {
1000 dev_err(dev, "cannot get platform resources for msi interrupt\n");
1001 err = -ENOENT;
1002 goto err_irq1;
1003 }
1004 pcie->msi.irq1 = i;
1005
1006 i = irq_of_parse_and_map(dev->of_node, 1);
1007 if (!i) {
1008 dev_err(dev, "cannot get platform resources for msi interrupt\n");
1009 err = -ENOENT;
1010 goto err_irq2;
1011 }
1012 pcie->msi.irq2 = i;
1013
1014 return 0;
1015
1016 err_irq2:
1017 irq_dispose_mapping(pcie->msi.irq1);
1018 err_irq1:
1019 return err;
1020 }
1021
rcar_pcie_inbound_ranges(struct rcar_pcie * pcie,struct of_pci_range * range,int * index)1022 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
1023 struct of_pci_range *range,
1024 int *index)
1025 {
1026 u64 restype = range->flags;
1027 u64 cpu_addr = range->cpu_addr;
1028 u64 cpu_end = range->cpu_addr + range->size;
1029 u64 pci_addr = range->pci_addr;
1030 u32 flags = LAM_64BIT | LAR_ENABLE;
1031 u64 mask;
1032 u64 size;
1033 int idx = *index;
1034
1035 if (restype & IORESOURCE_PREFETCH)
1036 flags |= LAM_PREFETCH;
1037
1038 /*
1039 * If the size of the range is larger than the alignment of the start
1040 * address, we have to use multiple entries to perform the mapping.
1041 */
1042 if (cpu_addr > 0) {
1043 unsigned long nr_zeros = __ffs64(cpu_addr);
1044 u64 alignment = 1ULL << nr_zeros;
1045
1046 size = min(range->size, alignment);
1047 } else {
1048 size = range->size;
1049 }
1050 /* Hardware supports max 4GiB inbound region */
1051 size = min(size, 1ULL << 32);
1052
1053 mask = roundup_pow_of_two(size) - 1;
1054 mask &= ~0xf;
1055
1056 while (cpu_addr < cpu_end) {
1057 /*
1058 * Set up 64-bit inbound regions as the range parser doesn't
1059 * distinguish between 32 and 64-bit types.
1060 */
1061 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr),
1062 PCIEPRAR(idx));
1063 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
1064 rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags,
1065 PCIELAMR(idx));
1066
1067 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr),
1068 PCIEPRAR(idx + 1));
1069 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr),
1070 PCIELAR(idx + 1));
1071 rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
1072
1073 pci_addr += size;
1074 cpu_addr += size;
1075 idx += 2;
1076
1077 if (idx > MAX_NR_INBOUND_MAPS) {
1078 dev_err(pcie->dev, "Failed to map inbound regions!\n");
1079 return -EINVAL;
1080 }
1081 }
1082 *index = idx;
1083
1084 return 0;
1085 }
1086
rcar_pcie_parse_map_dma_ranges(struct rcar_pcie * pcie,struct device_node * np)1087 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
1088 struct device_node *np)
1089 {
1090 struct of_pci_range range;
1091 struct of_pci_range_parser parser;
1092 int index = 0;
1093 int err;
1094
1095 if (of_pci_dma_range_parser_init(&parser, np))
1096 return -EINVAL;
1097
1098 /* Get the dma-ranges from DT */
1099 for_each_of_pci_range(&parser, &range) {
1100 u64 end = range.cpu_addr + range.size - 1;
1101
1102 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
1103 range.flags, range.cpu_addr, end, range.pci_addr);
1104
1105 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
1106 if (err)
1107 return err;
1108 }
1109
1110 return 0;
1111 }
1112
1113 static const struct of_device_id rcar_pcie_of_match[] = {
1114 { .compatible = "renesas,pcie-r8a7779",
1115 .data = rcar_pcie_phy_init_h1 },
1116 { .compatible = "renesas,pcie-r8a7790",
1117 .data = rcar_pcie_phy_init_gen2 },
1118 { .compatible = "renesas,pcie-r8a7791",
1119 .data = rcar_pcie_phy_init_gen2 },
1120 { .compatible = "renesas,pcie-rcar-gen2",
1121 .data = rcar_pcie_phy_init_gen2 },
1122 { .compatible = "renesas,pcie-r8a7795",
1123 .data = rcar_pcie_phy_init_gen3 },
1124 { .compatible = "renesas,pcie-rcar-gen3",
1125 .data = rcar_pcie_phy_init_gen3 },
1126 {},
1127 };
1128
rcar_pcie_probe(struct platform_device * pdev)1129 static int rcar_pcie_probe(struct platform_device *pdev)
1130 {
1131 struct device *dev = &pdev->dev;
1132 struct rcar_pcie *pcie;
1133 unsigned int data;
1134 int err;
1135 int (*phy_init_fn)(struct rcar_pcie *);
1136 struct pci_host_bridge *bridge;
1137
1138 bridge = pci_alloc_host_bridge(sizeof(*pcie));
1139 if (!bridge)
1140 return -ENOMEM;
1141
1142 pcie = pci_host_bridge_priv(bridge);
1143
1144 pcie->dev = dev;
1145 platform_set_drvdata(pdev, pcie);
1146
1147 err = pci_parse_request_of_pci_ranges(dev, &pcie->resources, NULL);
1148 if (err)
1149 goto err_free_bridge;
1150
1151 pm_runtime_enable(pcie->dev);
1152 err = pm_runtime_get_sync(pcie->dev);
1153 if (err < 0) {
1154 dev_err(pcie->dev, "pm_runtime_get_sync failed\n");
1155 goto err_pm_disable;
1156 }
1157
1158 err = rcar_pcie_get_resources(pcie);
1159 if (err < 0) {
1160 dev_err(dev, "failed to request resources: %d\n", err);
1161 goto err_pm_put;
1162 }
1163
1164 err = clk_prepare_enable(pcie->bus_clk);
1165 if (err) {
1166 dev_err(dev, "failed to enable bus clock: %d\n", err);
1167 goto err_unmap_msi_irqs;
1168 }
1169
1170 err = rcar_pcie_parse_map_dma_ranges(pcie, dev->of_node);
1171 if (err)
1172 goto err_clk_disable;
1173
1174 phy_init_fn = of_device_get_match_data(dev);
1175 err = phy_init_fn(pcie);
1176 if (err) {
1177 dev_err(dev, "failed to init PCIe PHY\n");
1178 goto err_clk_disable;
1179 }
1180
1181 /* Failure to get a link might just be that no cards are inserted */
1182 if (rcar_pcie_hw_init(pcie)) {
1183 dev_info(dev, "PCIe link down\n");
1184 err = -ENODEV;
1185 goto err_phy_shutdown;
1186 }
1187
1188 data = rcar_pci_read_reg(pcie, MACSR);
1189 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
1190
1191 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1192 err = rcar_pcie_enable_msi(pcie);
1193 if (err < 0) {
1194 dev_err(dev,
1195 "failed to enable MSI support: %d\n",
1196 err);
1197 goto err_phy_shutdown;
1198 }
1199 }
1200
1201 err = rcar_pcie_enable(pcie);
1202 if (err)
1203 goto err_msi_teardown;
1204
1205 return 0;
1206
1207 err_msi_teardown:
1208 if (IS_ENABLED(CONFIG_PCI_MSI))
1209 rcar_pcie_teardown_msi(pcie);
1210
1211 err_phy_shutdown:
1212 if (pcie->phy) {
1213 phy_power_off(pcie->phy);
1214 phy_exit(pcie->phy);
1215 }
1216
1217 err_clk_disable:
1218 clk_disable_unprepare(pcie->bus_clk);
1219
1220 err_unmap_msi_irqs:
1221 irq_dispose_mapping(pcie->msi.irq2);
1222 irq_dispose_mapping(pcie->msi.irq1);
1223
1224 err_pm_put:
1225 pm_runtime_put(dev);
1226
1227 err_pm_disable:
1228 pm_runtime_disable(dev);
1229 pci_free_resource_list(&pcie->resources);
1230
1231 err_free_bridge:
1232 pci_free_host_bridge(bridge);
1233
1234 return err;
1235 }
1236
rcar_pcie_resume_noirq(struct device * dev)1237 static int rcar_pcie_resume_noirq(struct device *dev)
1238 {
1239 struct rcar_pcie *pcie = dev_get_drvdata(dev);
1240
1241 if (rcar_pci_read_reg(pcie, PMSR) &&
1242 !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN))
1243 return 0;
1244
1245 /* Re-establish the PCIe link */
1246 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
1247 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
1248 return rcar_pcie_wait_for_dl(pcie);
1249 }
1250
1251 static const struct dev_pm_ops rcar_pcie_pm_ops = {
1252 .resume_noirq = rcar_pcie_resume_noirq,
1253 };
1254
1255 static struct platform_driver rcar_pcie_driver = {
1256 .driver = {
1257 .name = "rcar-pcie",
1258 .of_match_table = rcar_pcie_of_match,
1259 .pm = &rcar_pcie_pm_ops,
1260 .suppress_bind_attrs = true,
1261 },
1262 .probe = rcar_pcie_probe,
1263 };
1264 builtin_platform_driver(rcar_pcie_driver);
1265