Searched full:rams (Results 1 – 25 of 53) sorted by relevance
123
24 …t counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
8 …t counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
19 instruction RAMs, some internal peripheral modules to facilitate industrial35 acts on a primary Data RAM (there are usually 2 Data RAMs) at its address92 The various Data RAMs within a single PRU-ICSS unit are represented as a
165 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */167 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */168 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
4 tristate "I2C EEPROMs / RAMs / ROMs from most vendors"
263 Single Cycle RAMS to store Fast Path Code273 Single Cycle RAMS to store Fast Path Data
266 Single Cycle RAMS to store Fast Path Code277 Single Cycle RAMS to store Fast Path Data
5 tristate "I2C EEPROMs / RAMs / ROMs from most vendors"
154 This microcode relocates SMC1 and SMC2 parameter RAMs at
185 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */187 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */188 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
172 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */174 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */175 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
218 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */220 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */221 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
250 * Custom function to translate a DSP device address (internal RAMs only) to a251 * kernel virtual address. The DSPs can access their RAMs at either an internal
242 * Custom function to translate a DSP device address (internal RAMs only) to a243 * kernel virtual address. The DSPs can access their RAMs at either an internal
224 * internal RAMs. The .prepare() ops is invoked by remoteproc core before any350 * Custom function to translate a DSP device address (internal RAMs only) to a351 * kernel virtual address. The DSPs can access their RAMs at either an internal
44 - arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
242 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */244 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */245 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
285 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */287 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */288 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
284 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */286 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */287 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/