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/kernel/linux/linux-5.10/Documentation/riscv/
Dpatch-acceptance.rst1 .. SPDX-License-Identifier: GPL-2.0
7 --------
8 The RISC-V instruction set architecture is developed in the open:
9 in-progress drafts are available for all to review and to experiment
11 during the development process - sometimes in ways that are
13 challenge for RISC-V Linux maintenance. Linux maintainers disapprove
14 of churn, and the Linux development process prefers well-reviewed and
16 principles to the RISC-V-related code that will be accepted for
20 -------------------------
23 "Frozen" or "Ratified" by the RISC-V Foundation. (Developers may, of
[all …]
Dboot-image-header.rst2 Boot image header in RISC-V Linux
8 This document only describes the boot image header details for RISC-V Linux.
13 The following 64-byte header is present in decompressed Linux kernel image::
28 ARM64 header. Thus, both ARM64 & RISC-V header can be combined into one common
34 - This header can also be reused to support EFI stub for RISC-V in future. EFI
40 - version field indicate header version number
50 - The "magic" field is deprecated as of version 0.2. In a future
55 - In current header, the flags field has only one field.
61 - Image size is mandatory for boot loader to load kernel image. Booting will
/kernel/linux/linux-5.10/Documentation/translations/it_IT/riscv/
Dpatch-acceptance.rst1 .. include:: ../disclaimer-ita.rst
3 :Original: :doc:`../../../riscv/patch-acceptance`
10 ------------
12 L'insieme di istruzioni RISC-V sono sviluppate in modo aperto: le
15 dei nuovi moduli o estensioni possono cambiare in fase di sviluppo - a
18 supporto RISC-V nel kernel Linux. I manutentori Linux non amano
22 relativo all'architettura RISC-V che verrà accettato per l'inclusione
26 -------------------------------------------------------------------------
29 RISC-V li classifica come "Frozen" o "Retified". (Ovviamente, gli
33 In aggiunta, la specifica RISC-V permette agli implementatori di
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/kernel/liteos_m/targets/riscv_nuclei_demo_soc_gcc/GCC/
Dliteos_m.mk12 C_INCLUDES += -I$(LITEOSTOPDIR)/utils \
13 -I$(LITEOSTOPDIR)/kernel/include \
14 -I$(LITEOSTOPDIR)/components/cpup \
15 -I$(LITEOSTOPDIR)/components/los_backtrace \
16 -I$(LITEOSTOPDIR)/components/power
19 C_INCLUDES += -I$(LITEOSTOPDIR)/../../third_party/bounds_checking_function/include \
20 -I$(LITEOSTOPDIR)/../../third_party/bounds_checking_function/src
25 C_INCLUDES += -I$(LITEOSTOPDIR)/arch/risc-v/nuclei/gcc/nmsis/Core/Include \
26 -I$(LITEOSTOPDIR)/arch/risc-v/nuclei/gcc/nmsis/DSP/Include \
27 -I$(LITEOSTOPDIR)/arch/risc-v/nuclei/gcc/nmsis/NN/Include
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/kernel/liteos_m/targets/riscv_nuclei_gd32vf103_soc_gcc/GCC/
Dliteos_m.mk12 C_INCLUDES += -I$(LITEOSTOPDIR)/utils \
13 -I$(LITEOSTOPDIR)/kernel/include \
14 -I$(LITEOSTOPDIR)/components/cpup \
15 -I$(LITEOSTOPDIR)/components/backtrace \
16 -I$(LITEOSTOPDIR)/components/power
19 C_INCLUDES += -I$(LITEOSTOPDIR)/../../third_party/bounds_checking_function/include \
20 -I$(LITEOSTOPDIR)/../../third_party/bounds_checking_function/src
25 C_INCLUDES += -I$(LITEOSTOPDIR)/arch/risc-v/nuclei/gcc/nmsis/Core/Include \
26 -I$(LITEOSTOPDIR)/arch/risc-v/nuclei/gcc/nmsis/DSP/Include \
27 -I$(LITEOSTOPDIR)/arch/risc-v/nuclei/gcc/nmsis/NN/Include
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/riscv/
Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 This document uses some terminology common to the RISC-V community
18 mandated by the RISC-V ISA: a PC and some registers. This
28 - items:
29 - enum:
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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/
Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
28 - #interrupt-cells : should be <1>. The interrupt sources are defined by the
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
28 - #interrupt-cells : should be <1>. The interrupt sources are defined by the
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/riscv/
Dcpus.txt2 RISC-V CPU Bindings
13 with updates for 32-bit and 64-bit RISC-V systems provided in this document.
19 This document uses some terminology common to the RISC-V community that is not
23 the RISC-V ISA: a PC and some registers. This terminology is designed to
33 The RISC-V architecture, in accordance with the Devicetree Specification,
37 - cpus node
45 - #address-cells
49 - #size-cells
54 - cpu node
60 - device_type
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/kernel/linux/linux-5.10/arch/riscv/kernel/
Dperf_callchain.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2019 Hangzhou C-SKY Microsystems co.,ltd. */
23 (unsigned long *)(fp - sizeof(struct stackframe)); in user_backtrace()
53 * $ perf record -e cpu-clock --call-graph fp ./program
54 * $ perf report --call-graph
56 * On RISC-V platform, the program being sampled and the C library
57 * need to be compiled with -fno-omit-frame-pointer, otherwise
65 /* RISC-V does not support perf in guest mode. */ in perf_callchain_user()
66 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) in perf_callchain_user()
69 fp = regs->s0; in perf_callchain_user()
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Dcpu.c1 // SPDX-License-Identifier: GPL-2.0-only
12 * Returns the hart ID of the given device tree node, or -ENODEV if the node
13 * isn't an enabled and valid RISC-V hart node.
22 return -ENODEV; in riscv_of_processor_hartid()
27 return -ENODEV; in riscv_of_processor_hartid()
32 return -ENODEV; in riscv_of_processor_hartid()
37 return -ENODEV; in riscv_of_processor_hartid()
39 if (isa[0] != 'r' || isa[1] != 'v') { in riscv_of_processor_hartid()
41 return -ENODEV; in riscv_of_processor_hartid()
51 * RISC-V core (HART) node and extract the cpuid from it.
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/kernel/liteos_m/targets/riscv_nuclei_gd32vf103_soc_gcc/SoC/gd32vf103/Common/Source/Drivers/
Dgd32vf103_pmu.c5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
54 \arg PMU_LVDT_0: voltage threshold is 2.2V
55 \arg PMU_LVDT_1: voltage threshold is 2.3V
56 \arg PMU_LVDT_2: voltage threshold is 2.4V
57 \arg PMU_LVDT_3: voltage threshold is 2.5V
58 \arg PMU_LVDT_4: voltage threshold is 2.6V
59 \arg PMU_LVDT_5: voltage threshold is 2.7V
60 \arg PMU_LVDT_6: voltage threshold is 2.8V
61 \arg PMU_LVDT_7: voltage threshold is 2.9V
100 /* clear sleepdeep bit of RISC-V system control register */ in pmu_to_sleepmode()
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/kernel/linux/linux-5.10/drivers/media/pci/cx88/
Dcx88-alsa.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include "cx88-reg.h"
22 #include <linux/dma-mapping.h>
37 chip->core->name, ##arg); \
41 * Data type declarations - Can be moded to a header file later
46 struct cx88_riscmem risc; member
81 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
116 struct cx88_audio_buffer *buf = chip->buf; in _cx88_start_audio_dma()
117 struct cx88_core *core = chip->core; in _cx88_start_audio_dma()
120 /* Make sure RISC/FIFO are off before changing FIFO/RISC settings */ in _cx88_start_audio_dma()
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/kernel/linux/linux-4.19/drivers/media/pci/cx88/
Dcx88-alsa.c23 #include "cx88-reg.h"
31 #include <linux/dma-mapping.h>
46 chip->core->name, ##arg); \
50 * Data type declarations - Can be moded to a header file later
55 struct cx88_riscmem risc; member
90 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
125 struct cx88_audio_buffer *buf = chip->buf; in _cx88_start_audio_dma()
126 struct cx88_core *core = chip->core; in _cx88_start_audio_dma()
129 /* Make sure RISC/FIFO are off before changing FIFO/RISC settings */ in _cx88_start_audio_dma()
132 /* setup fifo + format - out channel */ in _cx88_start_audio_dma()
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/kernel/linux/linux-5.10/arch/riscv/include/asm/
Dpci.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <linux/dma-mapping.h>
18 /* RISC-V shim does not initialize PCI bus */
26 /* no legacy IRQ on risc-v */ in pci_get_legacy_ide_irq()
27 return -ENODEV; in pci_get_legacy_ide_irq()
/kernel/linux/linux-4.19/arch/riscv/include/uapi/asm/
Dsyscalls.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017-2018 SiFive
13 * Allows the instruction cache to be flushed from userspace. Despite RISC-V
18 * thread->hart mappings), so we've defined a RISC-V specific system call to
/kernel/linux/linux-4.19/arch/riscv/include/asm/
Dpci.h19 #include <linux/dma-mapping.h>
26 /* RISC-V shim does not initialize PCI bus */
34 /* no legacy IRQ on risc-v */ in pci_get_legacy_ide_irq()
35 return -ENODEV; in pci_get_legacy_ide_irq()
/kernel/liteos_m/
DREADME.md1 # LiteOS-M Kernel<a name="EN-US_TOPIC_0000001096757661"></a>
3 - [Introduction](#section11660541593)
4 - [Directory Structure](#section161941989596)
5 - [Constraints](#section119744591305)
6 - [Usage](#section3732185231214)
7 - [Contribution](#section1371123476307)
8 - [Repositories Involved](#section1371113476307)
12 …-M is a lightweight operating system kernel designed for the Internet of Things (IoT) field. It fe…
13 **Figure1** shows the architecture of the LiteOS-M kernel.
15 **Figure 1** Architecture of the OpenHarmony LiteOS-M kernel<a name="fig0865152210223"></a>
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/kernel/linux/linux-5.10/drivers/media/pci/cx23885/
Dcx23885-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 #include "altera-ci.h"
25 #include "cx23888-ir.h"
26 #include "cx23885-ir.h"
27 #include "cx23885-av.h"
28 #include "cx23885-input.h"
38 * encountered is "mpeg risc op code error". Only Ryzen platforms employ
45 …PARM_DESC(dma_reset_workaround, "periodic RiSC dma engine reset; 0-force disable, 1-driver detect …
51 static unsigned int card[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
63 #define NO_SYNC_LINE (-1U)
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/kernel/linux/linux-5.10/tools/arch/riscv/include/uapi/asm/
Dunistd.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
23 #include <asm-generic/unistd.h>
26 * Allows the instruction cache to be flushed from userspace. Despite RISC-V
31 * thread->hart mappings), so we've defined a RISC-V specific system call to
/kernel/linux/linux-5.10/arch/riscv/include/uapi/asm/
Dunistd.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
25 #include <asm-generic/unistd.h>
28 * Allows the instruction cache to be flushed from userspace. Despite RISC-V
33 * thread->hart mappings), so we've defined a RISC-V specific system call to
/kernel/linux/linux-4.19/drivers/media/pci/cx23885/
Dcx23885-core.c34 #include "altera-ci.h"
35 #include "cx23888-ir.h"
36 #include "cx23885-ir.h"
37 #include "cx23885-av.h"
38 #include "cx23885-input.h"
48 * encountered is "mpeg risc op code error". Only Ryzen platforms employ
55 …PARM_DESC(dma_reset_workaround, "periodic RiSC dma engine reset; 0-force disable, 1-driver detect …
61 static unsigned int card[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
73 #define NO_SYNC_LINE (-1U)
320 spin_lock_irqsave(&dev->pci_irqmask_lock, flags); in cx23885_irq_add()
[all …]
/kernel/linux/linux-5.10/drivers/clocksource/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
164 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
187 32-bit free running decrementing counters.
241 bool "Integrator-AP timer driver" if COMPILE_TEST
244 Enables support for the Integrator-AP timer.
277 available on many OMAP-like platforms.
286 It has a 64-bit counter with update rate up to 1000MHz.
287 This counter is accessed via couple of 32-bit memory-mapped registers.
306 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
310 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/
Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
[all …]
/kernel/linux/linux-5.10/drivers/irqchip/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
216 bool "J-Core integrated AIC" if COMPILE_TEST
220 Support for the J-Core integrated AIC.
231 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
234 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
239 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
274 tristate "TS-4800 IRQ controller"
279 Support for the TS-4800 FPGA IRQ controller
443 bool "C-SKY Multi Processor Interrupt Controller"
446 Say yes here to enable C-SKY SMP interrupt controller driver used
[all …]

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