1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2017-2018 SiFive 4 */ 5 6 /* 7 * There is explicitly no include guard here because this file is expected to 8 * be included multiple times in order to define the syscall macros via 9 * __SYSCALL. 10 */ 11 12 /* 13 * Allows the instruction cache to be flushed from userspace. Despite RISC-V 14 * having a direct 'fence.i' instruction available to userspace (which we 15 * can't trap!), that's not actually viable when running on Linux because the 16 * kernel might schedule a process on another hart. There is no way for 17 * userspace to handle this without invoking the kernel (as it doesn't know the 18 * thread->hart mappings), so we've defined a RISC-V specific system call to 19 * flush the instruction cache. 20 * 21 * __NR_riscv_flush_icache is defined to flush the instruction cache over an 22 * address range, with the flush applying to either all threads or just the 23 * caller. We don't currently do anything with the address range, that's just 24 * in there for forwards compatibility. 25 */ 26 #ifndef __NR_riscv_flush_icache 27 #define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15) 28 #endif 29 __SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache) 30