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/kernel/linux/linux-4.19/Documentation/vm/
D00-INDEX1 00-INDEX
2 - this file.
3 active_mm.rst
4 - An explanation from Linus about tsk->active_mm vs tsk->mm.
5 balance.rst
6 - various information on memory balancing.
7 cleancache.rst
8 - Intro to cleancache and page-granularity victim cache.
9 frontswap.rst
10 - Outline frontswap, part of the transcendent memory frontend.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/
Drenesas,rst.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/reset/renesas,rst.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Renesas R-Car and RZ/G Reset Controller
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
14 The R-Car and RZ/G Reset Controllers provide reset control, and implement the
16 - Latching of the levels on mode pins when PRESET# is negated,
17 - Mode monitoring register,
[all …]
/kernel/linux/linux-4.19/drivers/reset/
Dreset-hsdk.c17 #include <linux/reset-controller.h>
52 static void hsdk_reset_config(struct hsdk_rst *rst, unsigned long id) in hsdk_reset_config() argument
54 writel(rst_map[id], rst->regs_ctl + CGU_SYS_RST_CTRL); in hsdk_reset_config()
57 static int hsdk_reset_do(struct hsdk_rst *rst) in hsdk_reset_do() argument
61 reg = readl(rst->regs_rst + CGU_IP_SW_RESET); in hsdk_reset_do()
65 writel(reg, rst->regs_rst + CGU_IP_SW_RESET); in hsdk_reset_do()
68 return readl_poll_timeout_atomic(rst->regs_rst + CGU_IP_SW_RESET, reg, in hsdk_reset_do()
75 struct hsdk_rst *rst = to_hsdk_rst(rcdev); in hsdk_reset_reset() local
79 spin_lock_irqsave(&rst->lock, flags); in hsdk_reset_reset()
80 hsdk_reset_config(rst, id); in hsdk_reset_reset()
[all …]
Dreset-axs10x.c15 #include <linux/reset-controller.h>
30 struct axs10x_rst *rst = to_axs10x_rst(rcdev); in axs10x_reset_reset() local
33 spin_lock_irqsave(&rst->lock, flags); in axs10x_reset_reset()
34 writel(BIT(id), rst->regs_rst); in axs10x_reset_reset()
35 spin_unlock_irqrestore(&rst->lock, flags); in axs10x_reset_reset()
46 struct axs10x_rst *rst; in axs10x_reset_probe() local
49 rst = devm_kzalloc(&pdev->dev, sizeof(*rst), GFP_KERNEL); in axs10x_reset_probe()
50 if (!rst) in axs10x_reset_probe()
51 return -ENOMEM; in axs10x_reset_probe()
54 rst->regs_rst = devm_ioremap_resource(&pdev->dev, mem); in axs10x_reset_probe()
[all …]
/kernel/linux/linux-5.10/drivers/reset/
Dreset-hsdk.c17 #include <linux/reset-controller.h>
52 static void hsdk_reset_config(struct hsdk_rst *rst, unsigned long id) in hsdk_reset_config() argument
54 writel(rst_map[id], rst->regs_ctl + CGU_SYS_RST_CTRL); in hsdk_reset_config()
57 static int hsdk_reset_do(struct hsdk_rst *rst) in hsdk_reset_do() argument
61 reg = readl(rst->regs_rst + CGU_IP_SW_RESET); in hsdk_reset_do()
65 writel(reg, rst->regs_rst + CGU_IP_SW_RESET); in hsdk_reset_do()
68 return readl_poll_timeout_atomic(rst->regs_rst + CGU_IP_SW_RESET, reg, in hsdk_reset_do()
75 struct hsdk_rst *rst = to_hsdk_rst(rcdev); in hsdk_reset_reset() local
79 spin_lock_irqsave(&rst->lock, flags); in hsdk_reset_reset()
80 hsdk_reset_config(rst, id); in hsdk_reset_reset()
[all …]
Dreset-axs10x.c15 #include <linux/reset-controller.h>
30 struct axs10x_rst *rst = to_axs10x_rst(rcdev); in axs10x_reset_reset() local
33 spin_lock_irqsave(&rst->lock, flags); in axs10x_reset_reset()
34 writel(BIT(id), rst->regs_rst); in axs10x_reset_reset()
35 spin_unlock_irqrestore(&rst->lock, flags); in axs10x_reset_reset()
46 struct axs10x_rst *rst; in axs10x_reset_probe() local
49 rst = devm_kzalloc(&pdev->dev, sizeof(*rst), GFP_KERNEL); in axs10x_reset_probe()
50 if (!rst) in axs10x_reset_probe()
51 return -ENOMEM; in axs10x_reset_probe()
54 rst->regs_rst = devm_ioremap_resource(&pdev->dev, mem); in axs10x_reset_probe()
[all …]
/kernel/linux/linux-5.10/Documentation/userspace-api/media/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Rules to convert a .h file to inline RST documentation
5 SRC_DIR=$(srctree)/Documentation/userspace-api/media
6 PARSER = $(srctree)/Documentation/sphinx/parse-headers.pl
10 FILES = audio.h.rst ca.h.rst dmx.h.rst frontend.h.rst net.h.rst video.h.rst \
11 videodev2.h.rst media.h.rst cec.h.rst lirc.h.rst
24 $(BUILDDIR)/audio.h.rst: ${UAPI}/dvb/audio.h ${PARSER} $(SRC_DIR)/audio.h.rst.exceptions
27 $(BUILDDIR)/ca.h.rst: ${UAPI}/dvb/ca.h ${PARSER} $(SRC_DIR)/ca.h.rst.exceptions
30 $(BUILDDIR)/dmx.h.rst: ${UAPI}/dvb/dmx.h ${PARSER} $(SRC_DIR)/dmx.h.rst.exceptions
33 $(BUILDDIR)/frontend.h.rst: ${UAPI}/dvb/frontend.h ${PARSER} $(SRC_DIR)/frontend.h.rst.exceptions
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/reset/
Drenesas,rst.txt1 DT bindings for the Renesas R-Car and RZ/G Reset Controllers
3 The R-Car and RZ/G Reset Controllers provide reset control, and implement the
5 - Latching of the levels on mode pins when PRESET# is negated,
6 - Mode monitoring register,
7 - Reset control of peripheral devices (on R-Car Gen1),
8 - Watchdog timer (on R-Car Gen1),
9 - Register-based reset control and boot address registers for the various CPU
10 cores (on R-Car Gen2 and Gen3, and on RZ/G).
14 - compatible: Should be
15 - "renesas,<soctype>-reset-wdt" for R-Car Gen1,
[all …]
/kernel/linux/linux-4.19/Documentation/media/
DMakefile1 # Rules to convert a .h file to inline RST documentation
4 PARSER = $(srctree)/Documentation/sphinx/parse-headers.pl
8 FILES = audio.h.rst ca.h.rst dmx.h.rst frontend.h.rst net.h.rst video.h.rst \
9 videodev2.h.rst media.h.rst cec.h.rst lirc.h.rst
22 $(BUILDDIR)/audio.h.rst: ${UAPI}/dvb/audio.h ${PARSER} $(SRC_DIR)/audio.h.rst.exceptions
25 $(BUILDDIR)/ca.h.rst: ${UAPI}/dvb/ca.h ${PARSER} $(SRC_DIR)/ca.h.rst.exceptions
28 $(BUILDDIR)/dmx.h.rst: ${UAPI}/dvb/dmx.h ${PARSER} $(SRC_DIR)/dmx.h.rst.exceptions
31 $(BUILDDIR)/frontend.h.rst: ${UAPI}/dvb/frontend.h ${PARSER} $(SRC_DIR)/frontend.h.rst.exceptions
34 $(BUILDDIR)/net.h.rst: ${UAPI}/dvb/net.h ${PARSER} $(SRC_DIR)/net.h.rst.exceptions
37 $(BUILDDIR)/video.h.rst: ${UAPI}/dvb/video.h ${PARSER} $(SRC_DIR)/video.h.rst.exceptions
[all …]
/kernel/linux/linux-5.10/drivers/soc/renesas/
Drcar-rst.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen1 RESET/WDT, R-Car Gen2, Gen3, and RZ/G RST Driver
11 #include <linux/soc/renesas/rcar-rst.h>
45 /* RZ/G1 is handled like R-Car Gen2 */
46 { .compatible = "renesas,r8a7742-rst", .data = &rcar_rst_gen2 },
47 { .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },
48 { .compatible = "renesas,r8a7744-rst", .data = &rcar_rst_gen2 },
49 { .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },
50 { .compatible = "renesas,r8a77470-rst", .data = &rcar_rst_gen2 },
51 /* RZ/G2 is handled like R-Car Gen3 */
[all …]
/kernel/linux/linux-4.19/drivers/soc/renesas/
Drcar-rst.c2 * R-Car Gen1 RESET/WDT, R-Car Gen2, Gen3, and RZ/G RST Driver
14 #include <linux/soc/renesas/rcar-rst.h>
44 /* RZ/G is handled like R-Car Gen2 */
45 { .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },
46 { .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },
47 { .compatible = "renesas,r8a77470-rst", .data = &rcar_rst_gen2 },
48 /* R-Car Gen1 */
49 { .compatible = "renesas,r8a7778-reset-wdt", .data = &rcar_rst_gen1 },
50 { .compatible = "renesas,r8a7779-reset-wdt", .data = &rcar_rst_gen1 },
51 /* R-Car Gen2 */
[all …]
/kernel/linux/linux-5.10/drivers/memory/tegra/
Dtegra20.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/memory/tegra20-mc.h>
199 const struct tegra_mc_reset *rst) in tegra20_mc_hotreset_assert() argument
204 spin_lock_irqsave(&mc->lock, flags); in tegra20_mc_hotreset_assert()
206 value = mc_readl(mc, rst->reset); in tegra20_mc_hotreset_assert()
207 mc_writel(mc, value & ~BIT(rst->bit), rst->reset); in tegra20_mc_hotreset_assert()
209 spin_unlock_irqrestore(&mc->lock, flags); in tegra20_mc_hotreset_assert()
215 const struct tegra_mc_reset *rst) in tegra20_mc_hotreset_deassert() argument
220 spin_lock_irqsave(&mc->lock, flags); in tegra20_mc_hotreset_deassert()
222 value = mc_readl(mc, rst->reset); in tegra20_mc_hotreset_deassert()
[all …]
Dmc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
24 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
27 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
30 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
33 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
36 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
39 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
46 const struct tegra_mc_reset *rst) in tegra_mc_block_dma_common() argument
51 spin_lock_irqsave(&mc->lock, flags); in tegra_mc_block_dma_common()
[all …]
/kernel/linux/linux-4.19/drivers/memory/tegra/
Dtegra20.c9 #include <dt-bindings/memory/tegra20-mc.h>
202 const struct tegra_mc_reset *rst) in terga20_mc_hotreset_assert() argument
207 spin_lock_irqsave(&mc->lock, flags); in terga20_mc_hotreset_assert()
209 value = mc_readl(mc, rst->reset); in terga20_mc_hotreset_assert()
210 mc_writel(mc, value & ~BIT(rst->bit), rst->reset); in terga20_mc_hotreset_assert()
212 spin_unlock_irqrestore(&mc->lock, flags); in terga20_mc_hotreset_assert()
218 const struct tegra_mc_reset *rst) in terga20_mc_hotreset_deassert() argument
223 spin_lock_irqsave(&mc->lock, flags); in terga20_mc_hotreset_deassert()
225 value = mc_readl(mc, rst->reset); in terga20_mc_hotreset_deassert()
226 mc_writel(mc, value | BIT(rst->bit), rst->reset); in terga20_mc_hotreset_deassert()
[all …]
Dmc.c54 { .compatible = "nvidia,tegra20-mc", .data = &tegra20_mc_soc },
57 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
60 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
63 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
66 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
69 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
76 const struct tegra_mc_reset *rst) in terga_mc_block_dma_common() argument
81 spin_lock_irqsave(&mc->lock, flags); in terga_mc_block_dma_common()
83 value = mc_readl(mc, rst->control) | BIT(rst->bit); in terga_mc_block_dma_common()
84 mc_writel(mc, value, rst->control); in terga_mc_block_dma_common()
[all …]
/kernel/linux/linux-5.10/Documentation/sphinx-static/
Dtheme_overrides.css1 /* -*- coding: utf-8; mode: css -*-
10 font-family: serif;
12 font-size: 100%;
15 h1, h2, .rst-content .toctree-wrapper p.caption, h3, h4, h5, h6, legend {
16 font-family: sans-serif;
19 .wy-menu-vertical li.current a {
23 .wy-menu-vertical li.on a, .wy-menu-vertical li.current > a {
28 font-family: monospace;
30 font-size: 100%;
33 .wy-menu-vertical {
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/altera/
Dsocfpga_stratix10.dtsi17 /dts-v1/;
18 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
19 #include <dt-bindings/gpio/gpio.h>
20 #include <dt-bindings/clock/stratix10-clock.h>
23 compatible = "altr,socfpga-stratix10";
24 #address-cells = <2>;
25 #size-cells = <2>;
28 #address-cells = <1>;
29 #size-cells = <0>;
32 compatible = "arm,cortex-a53", "arm,armv8";
[all …]
/kernel/linux/linux-5.10/Documentation/filesystems/ext4/
Doverview.rst1 .. SPDX-License-Identifier: GPL-2.0
15 All fields in ext4 are written to disk in little-endian order. HOWEVER,
16 all fields in jbd2 (the journal) are written to disk in big-endian
19 .. include:: blocks.rst
20 .. include:: blockgroup.rst
21 .. include:: special_inodes.rst
22 .. include:: allocators.rst
23 .. include:: checksums.rst
24 .. include:: bigalloc.rst
25 .. include:: inlinedata.rst
[all …]
/kernel/linux/linux-4.19/Documentation/sphinx-static/
Dtheme_overrides.css1 /* -*- coding: utf-8; mode: css -*-
7 /* Interim: Code-blocks with line nos - lines and line numbers don't line up.
12 line-height: normal;
14 .rst-content .highlight > pre {
15 line-height: normal;
23 * tables with tons of columns, which need the full width of the view-port.
26 .wy-nav-content{max-width: none; }
30 * - Sequences of whitespace should collapse into a single whitespace.
31 * - make the overflow auto (scrollbar if needed)
32 * - align caption "left" ("center" is unsuitable on vast tables)
[all …]
/kernel/linux/linux-5.10/drivers/clk/qcom/
Dreset.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/reset-controller.h>
16 rcdev->ops->assert(rcdev, id); in qcom_reset()
18 rcdev->ops->deassert(rcdev, id); in qcom_reset()
25 struct qcom_reset_controller *rst; in qcom_reset_assert() local
29 rst = to_qcom_reset_controller(rcdev); in qcom_reset_assert()
30 map = &rst->reset_map[id]; in qcom_reset_assert()
31 mask = BIT(map->bit); in qcom_reset_assert()
33 return regmap_update_bits(rst->regmap, map->reg, mask, mask); in qcom_reset_assert()
39 struct qcom_reset_controller *rst; in qcom_reset_deassert() local
[all …]
/kernel/linux/linux-5.10/drivers/reset/sti/
Dreset-syscfg.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Inspired by mach-imx/src.c
17 #include "reset-syscfg.h"
20 * struct syscfg_reset_channel - Reset channel regmap configuration
31 * struct syscfg_reset_controller - A reset controller which groups together
35 * @rst: base reset controller structure.
41 struct reset_controller_dev rst; member
47 container_of(_rst, struct syscfg_reset_controller, rst)
52 struct syscfg_reset_controller *rst = to_syscfg_reset_controller(rcdev); in syscfg_reset_program_hw() local
54 u32 ctrl_val = rst->active_low ? !assert : !!assert; in syscfg_reset_program_hw()
[all …]
/kernel/linux/linux-4.19/drivers/reset/sti/
Dreset-syscfg.c5 * Inspired by mach-imx/src.c
21 #include "reset-syscfg.h"
38 * @rst: base reset controller structure.
44 struct reset_controller_dev rst; member
50 container_of(_rst, struct syscfg_reset_controller, rst)
55 struct syscfg_reset_controller *rst = to_syscfg_reset_controller(rcdev); in syscfg_reset_program_hw() local
57 u32 ctrl_val = rst->active_low ? !assert : !!assert; in syscfg_reset_program_hw()
60 if (idx >= rcdev->nr_resets) in syscfg_reset_program_hw()
61 return -EINVAL; in syscfg_reset_program_hw()
63 ch = &rst->channels[idx]; in syscfg_reset_program_hw()
[all …]
/kernel/linux/linux-5.10/Documentation/translations/zh_CN/process/
Dhowto.rst3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: :ref:`Documentation/process/howto.rst <process_howto>`
9 英文版维护者： Greg Kroah-Hartman <greg@kroah.com>
29 ----
41 - "The C Programming Language" by Kernighan and Ritchie [Prentice Hall]
43 - "Practical C Programming" by Steve Oualline [O'Reilly]
45 - "C: A Reference Manual" by Harbison and Steele [Prentice Hall]
62 --------
67 :ref:`Documentation/translations/zh_CN/process/license-rules.rst <cn_kernel_licensing>`
72 https://www.gnu.org/licenses/gpl-faq.html
[all …]
/kernel/linux/linux-4.19/Documentation/filesystems/ext4/ondisk/
Doverview.rst1 .. SPDX-License-Identifier: GPL-2.0
15 All fields in ext4 are written to disk in little-endian order. HOWEVER,
16 all fields in jbd2 (the journal) are written to disk in big-endian
19 .. include:: blocks.rst
20 .. include:: blockgroup.rst
21 .. include:: special_inodes.rst
22 .. include:: allocators.rst
23 .. include:: checksums.rst
24 .. include:: bigalloc.rst
25 .. include:: inlinedata.rst
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/intel/
Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/agilex-clock.h>
12 compatible = "intel,socfpga-agilex";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]

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