1/* 2 * Copyright Altera Corporation (C) 2015. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17/dts-v1/; 18#include <dt-bindings/reset/altr,rst-mgr-s10.h> 19#include <dt-bindings/gpio/gpio.h> 20#include <dt-bindings/clock/stratix10-clock.h> 21 22/ { 23 compatible = "altr,socfpga-stratix10"; 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 compatible = "arm,cortex-a53", "arm,armv8"; 33 device_type = "cpu"; 34 enable-method = "psci"; 35 reg = <0x0>; 36 }; 37 38 cpu1: cpu@1 { 39 compatible = "arm,cortex-a53", "arm,armv8"; 40 device_type = "cpu"; 41 enable-method = "psci"; 42 reg = <0x1>; 43 }; 44 45 cpu2: cpu@2 { 46 compatible = "arm,cortex-a53", "arm,armv8"; 47 device_type = "cpu"; 48 enable-method = "psci"; 49 reg = <0x2>; 50 }; 51 52 cpu3: cpu@3 { 53 compatible = "arm,cortex-a53", "arm,armv8"; 54 device_type = "cpu"; 55 enable-method = "psci"; 56 reg = <0x3>; 57 }; 58 }; 59 60 pmu { 61 compatible = "arm,armv8-pmuv3"; 62 interrupts = <0 170 4>, 63 <0 171 4>, 64 <0 172 4>, 65 <0 173 4>; 66 interrupt-affinity = <&cpu0>, 67 <&cpu1>, 68 <&cpu2>, 69 <&cpu3>; 70 interrupt-parent = <&intc>; 71 }; 72 73 psci { 74 compatible = "arm,psci-0.2"; 75 method = "smc"; 76 }; 77 78 intc: intc@fffc1000 { 79 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 80 #interrupt-cells = <3>; 81 interrupt-controller; 82 reg = <0x0 0xfffc1000 0x0 0x1000>, 83 <0x0 0xfffc2000 0x0 0x2000>, 84 <0x0 0xfffc4000 0x0 0x2000>, 85 <0x0 0xfffc6000 0x0 0x2000>; 86 }; 87 88 soc { 89 #address-cells = <1>; 90 #size-cells = <1>; 91 compatible = "simple-bus"; 92 device_type = "soc"; 93 interrupt-parent = <&intc>; 94 ranges = <0 0 0 0xffffffff>; 95 96 clkmgr: clock-controller@ffd10000 { 97 compatible = "intel,stratix10-clkmgr"; 98 reg = <0xffd10000 0x1000>; 99 #clock-cells = <1>; 100 }; 101 102 clocks { 103 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { 104 #clock-cells = <0>; 105 compatible = "fixed-clock"; 106 }; 107 108 cb_intosc_ls_clk: cb-intosc-ls-clk { 109 #clock-cells = <0>; 110 compatible = "fixed-clock"; 111 }; 112 113 f2s_free_clk: f2s-free-clk { 114 #clock-cells = <0>; 115 compatible = "fixed-clock"; 116 }; 117 118 osc1: osc1 { 119 #clock-cells = <0>; 120 compatible = "fixed-clock"; 121 }; 122 123 qspi_clk: qspi-clk { 124 #clock-cells = <0>; 125 compatible = "fixed-clock"; 126 clock-frequency = <200000000>; 127 }; 128 }; 129 130 gmac0: ethernet@ff800000 { 131 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 132 reg = <0xff800000 0x2000>; 133 interrupts = <0 90 4>; 134 interrupt-names = "macirq"; 135 mac-address = [00 00 00 00 00 00]; 136 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 137 reset-names = "stmmaceth", "stmmaceth-ocp"; 138 clocks = <&clkmgr STRATIX10_EMAC0_CLK>; 139 clock-names = "stmmaceth"; 140 tx-fifo-depth = <16384>; 141 rx-fifo-depth = <16384>; 142 snps,multicast-filter-bins = <256>; 143 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 144 status = "disabled"; 145 }; 146 147 gmac1: ethernet@ff802000 { 148 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 149 reg = <0xff802000 0x2000>; 150 interrupts = <0 91 4>; 151 interrupt-names = "macirq"; 152 mac-address = [00 00 00 00 00 00]; 153 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 154 reset-names = "stmmaceth", "stmmaceth-ocp"; 155 clocks = <&clkmgr STRATIX10_EMAC1_CLK>; 156 clock-names = "stmmaceth"; 157 tx-fifo-depth = <16384>; 158 rx-fifo-depth = <16384>; 159 snps,multicast-filter-bins = <256>; 160 altr,sysmgr-syscon = <&sysmgr 0x48 0>; 161 status = "disabled"; 162 }; 163 164 gmac2: ethernet@ff804000 { 165 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 166 reg = <0xff804000 0x2000>; 167 interrupts = <0 92 4>; 168 interrupt-names = "macirq"; 169 mac-address = [00 00 00 00 00 00]; 170 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 171 reset-names = "stmmaceth", "stmmaceth-ocp"; 172 clocks = <&clkmgr STRATIX10_EMAC2_CLK>; 173 clock-names = "stmmaceth"; 174 tx-fifo-depth = <16384>; 175 rx-fifo-depth = <16384>; 176 snps,multicast-filter-bins = <256>; 177 altr,sysmgr-syscon = <&sysmgr 0x4c 0>; 178 status = "disabled"; 179 }; 180 181 gpio0: gpio@ffc03200 { 182 #address-cells = <1>; 183 #size-cells = <0>; 184 compatible = "snps,dw-apb-gpio"; 185 reg = <0xffc03200 0x100>; 186 resets = <&rst GPIO0_RESET>; 187 status = "disabled"; 188 189 porta: gpio-controller@0 { 190 compatible = "snps,dw-apb-gpio-port"; 191 gpio-controller; 192 #gpio-cells = <2>; 193 snps,nr-gpios = <24>; 194 reg = <0>; 195 interrupt-controller; 196 #interrupt-cells = <2>; 197 interrupts = <0 110 4>; 198 }; 199 }; 200 201 gpio1: gpio@ffc03300 { 202 #address-cells = <1>; 203 #size-cells = <0>; 204 compatible = "snps,dw-apb-gpio"; 205 reg = <0xffc03300 0x100>; 206 resets = <&rst GPIO1_RESET>; 207 status = "disabled"; 208 209 portb: gpio-controller@0 { 210 compatible = "snps,dw-apb-gpio-port"; 211 gpio-controller; 212 #gpio-cells = <2>; 213 snps,nr-gpios = <24>; 214 reg = <0>; 215 interrupt-controller; 216 #interrupt-cells = <2>; 217 interrupts = <0 111 4>; 218 }; 219 }; 220 221 i2c0: i2c@ffc02800 { 222 #address-cells = <1>; 223 #size-cells = <0>; 224 compatible = "snps,designware-i2c"; 225 reg = <0xffc02800 0x100>; 226 interrupts = <0 103 4>; 227 resets = <&rst I2C0_RESET>; 228 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 229 status = "disabled"; 230 }; 231 232 i2c1: i2c@ffc02900 { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 compatible = "snps,designware-i2c"; 236 reg = <0xffc02900 0x100>; 237 interrupts = <0 104 4>; 238 resets = <&rst I2C1_RESET>; 239 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 240 status = "disabled"; 241 }; 242 243 i2c2: i2c@ffc02a00 { 244 #address-cells = <1>; 245 #size-cells = <0>; 246 compatible = "snps,designware-i2c"; 247 reg = <0xffc02a00 0x100>; 248 interrupts = <0 105 4>; 249 resets = <&rst I2C2_RESET>; 250 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 251 status = "disabled"; 252 }; 253 254 i2c3: i2c@ffc02b00 { 255 #address-cells = <1>; 256 #size-cells = <0>; 257 compatible = "snps,designware-i2c"; 258 reg = <0xffc02b00 0x100>; 259 interrupts = <0 106 4>; 260 resets = <&rst I2C3_RESET>; 261 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 262 status = "disabled"; 263 }; 264 265 i2c4: i2c@ffc02c00 { 266 #address-cells = <1>; 267 #size-cells = <0>; 268 compatible = "snps,designware-i2c"; 269 reg = <0xffc02c00 0x100>; 270 interrupts = <0 107 4>; 271 resets = <&rst I2C4_RESET>; 272 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 273 status = "disabled"; 274 }; 275 276 mmc: dwmmc0@ff808000 { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 compatible = "altr,socfpga-dw-mshc"; 280 reg = <0xff808000 0x1000>; 281 interrupts = <0 96 4>; 282 fifo-depth = <0x400>; 283 resets = <&rst SDMMC_RESET>; 284 reset-names = "reset"; 285 clocks = <&clkmgr STRATIX10_L4_MP_CLK>, 286 <&clkmgr STRATIX10_SDMMC_CLK>; 287 clock-names = "biu", "ciu"; 288 status = "disabled"; 289 }; 290 291 ocram: sram@ffe00000 { 292 compatible = "mmio-sram"; 293 reg = <0xffe00000 0x100000>; 294 }; 295 296 pdma: pdma@ffda0000 { 297 compatible = "arm,pl330", "arm,primecell"; 298 reg = <0xffda0000 0x1000>; 299 interrupts = <0 81 4>, 300 <0 82 4>, 301 <0 83 4>, 302 <0 84 4>, 303 <0 85 4>, 304 <0 86 4>, 305 <0 87 4>, 306 <0 88 4>, 307 <0 89 4>; 308 #dma-cells = <1>; 309 #dma-channels = <8>; 310 #dma-requests = <32>; 311 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 312 clock-names = "apb_pclk"; 313 }; 314 315 rst: rstmgr@ffd11000 { 316 #reset-cells = <1>; 317 compatible = "altr,rst-mgr"; 318 reg = <0xffd11000 0x1000>; 319 altr,modrst-offset = <0x20>; 320 }; 321 322 spi0: spi@ffda4000 { 323 compatible = "snps,dw-apb-ssi"; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 reg = <0xffda4000 0x1000>; 327 interrupts = <0 99 4>; 328 resets = <&rst SPIM0_RESET>; 329 reg-io-width = <4>; 330 num-cs = <4>; 331 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 332 status = "disabled"; 333 }; 334 335 spi1: spi@ffda5000 { 336 compatible = "snps,dw-apb-ssi"; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 reg = <0xffda5000 0x1000>; 340 interrupts = <0 100 4>; 341 resets = <&rst SPIM1_RESET>; 342 reg-io-width = <4>; 343 num-cs = <4>; 344 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 345 status = "disabled"; 346 }; 347 348 sysmgr: sysmgr@ffd12000 { 349 compatible = "altr,sys-mgr", "syscon"; 350 reg = <0xffd12000 0x228>; 351 }; 352 353 /* Local timer */ 354 timer { 355 compatible = "arm,armv8-timer"; 356 interrupts = <1 13 0xf08>, 357 <1 14 0xf08>, 358 <1 11 0xf08>, 359 <1 10 0xf08>; 360 }; 361 362 timer0: timer0@ffc03000 { 363 compatible = "snps,dw-apb-timer"; 364 interrupts = <0 113 4>; 365 reg = <0xffc03000 0x100>; 366 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 367 clock-names = "timer"; 368 }; 369 370 timer1: timer1@ffc03100 { 371 compatible = "snps,dw-apb-timer"; 372 interrupts = <0 114 4>; 373 reg = <0xffc03100 0x100>; 374 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 375 clock-names = "timer"; 376 }; 377 378 timer2: timer2@ffd00000 { 379 compatible = "snps,dw-apb-timer"; 380 interrupts = <0 115 4>; 381 reg = <0xffd00000 0x100>; 382 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 383 clock-names = "timer"; 384 }; 385 386 timer3: timer3@ffd00100 { 387 compatible = "snps,dw-apb-timer"; 388 interrupts = <0 116 4>; 389 reg = <0xffd00100 0x100>; 390 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 391 clock-names = "timer"; 392 }; 393 394 uart0: serial0@ffc02000 { 395 compatible = "snps,dw-apb-uart"; 396 reg = <0xffc02000 0x100>; 397 interrupts = <0 108 4>; 398 reg-shift = <2>; 399 reg-io-width = <4>; 400 resets = <&rst UART0_RESET>; 401 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 402 status = "disabled"; 403 }; 404 405 uart1: serial1@ffc02100 { 406 compatible = "snps,dw-apb-uart"; 407 reg = <0xffc02100 0x100>; 408 interrupts = <0 109 4>; 409 reg-shift = <2>; 410 reg-io-width = <4>; 411 resets = <&rst UART1_RESET>; 412 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 413 status = "disabled"; 414 }; 415 416 usbphy0: usbphy@0 { 417 #phy-cells = <0>; 418 compatible = "usb-nop-xceiv"; 419 status = "okay"; 420 }; 421 422 usb0: usb@ffb00000 { 423 compatible = "snps,dwc2"; 424 reg = <0xffb00000 0x40000>; 425 interrupts = <0 93 4>; 426 phys = <&usbphy0>; 427 phy-names = "usb2-phy"; 428 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 429 reset-names = "dwc2", "dwc2-ecc"; 430 clocks = <&clkmgr STRATIX10_USB_CLK>; 431 status = "disabled"; 432 }; 433 434 usb1: usb@ffb40000 { 435 compatible = "snps,dwc2"; 436 reg = <0xffb40000 0x40000>; 437 interrupts = <0 94 4>; 438 phys = <&usbphy0>; 439 phy-names = "usb2-phy"; 440 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 441 reset-names = "dwc2", "dwc2-ecc"; 442 clocks = <&clkmgr STRATIX10_USB_CLK>; 443 status = "disabled"; 444 }; 445 446 watchdog0: watchdog@ffd00200 { 447 compatible = "snps,dw-wdt"; 448 reg = <0xffd00200 0x100>; 449 interrupts = <0 117 4>; 450 resets = <&rst WATCHDOG0_RESET>; 451 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 452 status = "disabled"; 453 }; 454 455 watchdog1: watchdog@ffd00300 { 456 compatible = "snps,dw-wdt"; 457 reg = <0xffd00300 0x100>; 458 interrupts = <0 118 4>; 459 resets = <&rst WATCHDOG1_RESET>; 460 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 461 status = "disabled"; 462 }; 463 464 watchdog2: watchdog@ffd00400 { 465 compatible = "snps,dw-wdt"; 466 reg = <0xffd00400 0x100>; 467 interrupts = <0 125 4>; 468 resets = <&rst WATCHDOG2_RESET>; 469 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 470 status = "disabled"; 471 }; 472 473 watchdog3: watchdog@ffd00500 { 474 compatible = "snps,dw-wdt"; 475 reg = <0xffd00500 0x100>; 476 interrupts = <0 126 4>; 477 resets = <&rst WATCHDOG3_RESET>; 478 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 479 status = "disabled"; 480 }; 481 482 eccmgr { 483 compatible = "altr,socfpga-s10-ecc-manager"; 484 interrupts = <0 15 4>, <0 95 4>; 485 interrupt-controller; 486 #interrupt-cells = <2>; 487 488 sdramedac { 489 compatible = "altr,sdram-edac-s10"; 490 interrupts = <16 4>, <48 4>; 491 }; 492 }; 493 494 qspi: spi@ff8d2000 { 495 compatible = "cdns,qspi-nor"; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 reg = <0xff8d2000 0x100>, 499 <0xff900000 0x100000>; 500 interrupts = <0 3 4>; 501 cdns,fifo-depth = <128>; 502 cdns,fifo-width = <4>; 503 cdns,trigger-address = <0x00000000>; 504 clocks = <&qspi_clk>; 505 506 status = "disabled"; 507 }; 508 }; 509}; 510