| /kernel/linux/linux-5.10/include/kvm/ |
| D | arm_vgic.h | 97 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU
123 u8 source; /* GICv2 SGIs only */
124 u8 active_source; /* GICv2 SGIs only */
234 /* Wants SGIs without active state */
|
| /kernel/linux/linux-5.10/arch/arm64/kvm/vgic/ |
| D | vgic-mmio-v3.c | 121 /* Not a GICv4.1? No HW SGIs */ in vgic_mmio_write_v3_misc()
131 /* Switching HW SGIs? */ in vgic_mmio_write_v3_misc()
166 /* Not a GICv4.1? No HW SGIs */ in vgic_mmio_uaccess_write_v3_misc()
522 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
961 * @allow_group1: Does the sysreg access allow generation of G1 SGIs
963 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
1022 * An access targeting Group0 SGIs can only generate in vgic_v3_dispatch_sgi()
1023 * those, while an access targeting Group1 SGIs can in vgic_v3_dispatch_sgi()
|
| D | vgic.c | 93 /* SGIs and PPIs */ in vgic_get_irq()
596 /* SGIs and LPIs cannot be wired up to any device */ in kvm_vgic_set_owner()
772 /* GICv2 SGIs can count for more than one... */ in compute_ap_list_depth()
804 * If we have multi-SGIs in the pipeline, we need to in vgic_flush_lr_state()
|
| D | vgic-init.c | 199 * Enable and configure all SGIs to be edge-triggered and in kvm_vgic_vcpu_init()
212 /* SGIs */ in kvm_vgic_vcpu_init()
|
| D | vgic-mmio.c | 327 * GICv2 SGIs are terribly broken. We can't restore in vgic_uaccess_write_spending()
419 * More fun with GICv2 SGIs! If we're clearing one of them in vgic_uaccess_write_cpending()
723 * The configuration cannot be changed for SGIs in general, in vgic_mmio_write_config()
|
| /kernel/linux/linux-4.19/include/kvm/ |
| D | arm_vgic.h | 107 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU
133 u8 source; /* GICv2 SGIs only */
134 u8 active_source; /* GICv2 SGIs only */
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic.txt | 7 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
9 have PPIs or SGIs.
|
| D | ti,omap4-wugen-mpu | 20 - Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
|
| D | nvidia,tegra20-ictlr.txt | 27 - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,omap4-wugen-mpu | 20 - Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
|
| D | arm,gic.yaml | 17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
19 have PPIs or SGIs.
|
| D | nvidia,tegra20-ictlr.txt | 27 - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
|
| /kernel/linux/linux-4.19/virt/kvm/arm/vgic/ |
| D | vgic-mmio-v3.c | 447 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
904 * @allow_group1: Does the sysreg access allow generation of G1 SGIs
906 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
965 * An access targetting Group0 SGIs can only generate in vgic_v3_dispatch_sgi()
966 * those, while an access targetting Group1 SGIs can in vgic_v3_dispatch_sgi()
|
| D | vgic.c | 104 /* SGIs and PPIs */ in vgic_get_irq()
576 /* SGIs and LPIs cannot be wired up to any device */ in kvm_vgic_set_owner()
752 /* GICv2 SGIs can count for more than one... */ in compute_ap_list_depth()
783 * If we have multi-SGIs in the pipeline, we need to in vgic_flush_lr_state()
|
| D | vgic-init.c | 220 * Enable and configure all SGIs to be edge-triggered and in kvm_vgic_vcpu_init()
233 /* SGIs */ in kvm_vgic_vcpu_init()
|
| /kernel/linux/linux-4.19/drivers/irqchip/ |
| D | irq-hip04.c | 125 /* Interrupt configuration for SGIs can't be changed */ in hip04_irq_set_type()
336 /* Get the interrupt number and add 16 to skip over SGIs */ in hip04_irq_domain_xlate()
|
| D | irq-gic-common.c | 120 * Deactivate and disable all SPIs. Leave the PPI and SGIs in gic_dist_config()
|
| D | irq-gic.c | 298 /* Interrupt configuration for SGIs can't be changed */ in gic_set_type()
911 * Now let's migrate and clear any potential SGIs that might be in gic_migrate_target()
918 * for previously sent SGIs by us to other CPUs either. in gic_migrate_target()
995 /* Get the interrupt number and add 16 to skip over SGIs */ in gic_irq_domain_translate()
1139 * For primary GICs, skip over SGIs. in gic_init_bases()
|
| D | irq-gic-v3.c | 306 /* Interrupt configuration for SGIs can't be changed */ in gic_set_type()
624 /* Check all the CPUs have capable of sending SGIs to other CPUs */ in gic_cpu_sys_reg_init()
671 /* Configure SGIs/PPIs as non-secure Group-1 */ in gic_cpu_init()
894 /* SGIs are private to the core kernel */ in gic_irq_domain_map()
|
| D | irq-alpine-msi.c | 35 u32 num_spis; /* The number of SGIs for MSIs */
|
| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-hip04.c | 122 /* Interrupt configuration for SGIs can't be changed */ in hip04_irq_set_type()
333 /* Get the interrupt number and add 16 to skip over SGIs */ in hip04_irq_domain_xlate()
|
| D | irq-gic-common.c | 119 * Deactivate and disable all SPIs. Leave the PPI and SGIs in gic_dist_config()
|
| D | irq-gic.c | 299 /* Interrupt configuration for SGIs can't be changed */ in gic_set_type()
367 * works because we don't nest SGIs... in gic_handle_irq()
973 * Now let's migrate and clear any potential SGIs that might be in gic_migrate_target()
980 * for previously sent SGIs by us to other CPUs either. in gic_migrate_target()
1212 * For primary GICs, skip over SGIs. in gic_init_bases()
|
| D | irq-alpine-msi.c | 35 u32 num_spis; /* The number of SGIs for MSIs */
|
| D | irq-gic-v3.c | 579 /* Interrupt configuration for SGIs can't be changed */ in gic_set_type()
810 pr_info("Enabling SGIs without active state\n"); in gic_dist_init()
1056 /* Check all the CPUs have capable of sending SGIs to other CPUs */ in gic_cpu_sys_reg_init()
1111 /* Configure SGIs/PPIs as non-secure Group-1 */ in gic_cpu_init()
1219 /* Register all 8 non-secure SGIs */ in gic_smp_init()
|