Home
last modified time | relevance | path

Searched +full:super +full:- +full:speed (Results 1 – 25 of 272) sorted by relevance

1234567891011

/kernel/linux/linux-5.10/Documentation/hwmon/
Dnct6775.rst15 Addresses scanned: ISA address retrieved from Super I/O registers
19 * Nuvoton NCT5572D/NCT6771F/NCT6772F/NCT6775F/W83677HG-I
23 Addresses scanned: ISA address retrieved from Super I/O registers
31 Addresses scanned: ISA address retrieved from Super I/O registers
39 Addresses scanned: ISA address retrieved from Super I/O registers
47 Addresses scanned: ISA address retrieved from Super I/O registers
55 Addresses scanned: ISA address retrieved from Super I/O registers
63 Addresses scanned: ISA address retrieved from Super I/O registers
71 Addresses scanned: ISA address retrieved from Super I/O registers
79 Addresses scanned: ISA address retrieved from Super I/O registers
[all …]
Df71882fg.rst10 Addresses scanned: none, address read from Super I/O config space
18 Addresses scanned: none, address read from Super I/O config space
26 Addresses scanned: none, address read from Super I/O config space
34 Addresses scanned: none, address read from Super I/O config space
42 Addresses scanned: none, address read from Super I/O config space
50 Addresses scanned: none, address read from Super I/O config space
58 Addresses scanned: none, address read from Super I/O config space
66 Addresses scanned: none, address read from Super I/O config space
74 Addresses scanned: none, address read from Super I/O config space
82 Addresses scanned: none, address read from Super I/O config space
[all …]
Dit87.rst10 Addresses scanned: from Super I/O config space (8 I/O ports)
18 Addresses scanned: from Super I/O config space (8 I/O ports)
24 Addresses scanned: from Super I/O config space (8 I/O ports)
32 Addresses scanned: from Super I/O config space (8 I/O ports)
40 Addresses scanned: from Super I/O config space (8 I/O ports)
48 Addresses scanned: from Super I/O config space (8 I/O ports)
56 Addresses scanned: from Super I/O config space (8 I/O ports)
64 Addresses scanned: from Super I/O config space (8 I/O ports)
72 Addresses scanned: from Super I/O config space (8 I/O ports)
80 Addresses scanned: from Super I/O config space (8 I/O ports)
[all …]
Dw83627ehf.rst10 Addresses scanned: ISA address retrieved from Super I/O registers
18 Addresses scanned: ISA address retrieved from Super I/O registers
22 * Winbond W83627DHG-P
26 Addresses scanned: ISA address retrieved from Super I/O registers
34 Addresses scanned: ISA address retrieved from Super I/O registers
42 Addresses scanned: ISA address retrieved from Super I/O registers
46 * Winbond W83667HG-B
50 Addresses scanned: ISA address retrieved from Super I/O registers
54 * Nuvoton NCT6775F/W83667HG-I
58 Addresses scanned: ISA address retrieved from Super I/O registers
[all …]
Df71805f.rst10 Addresses scanned: none, address read from Super I/O config space
18 Addresses scanned: none, address read from Super I/O config space
26 Addresses scanned: none, address read from Super I/O config space
44 -----------
46 The Fintek F71805F/FG Super I/O chip includes complete hardware monitoring
53 The Fintek F71872F/FG Super I/O chip is almost the same, with two
57 The Fintek F71806F/FG Super-I/O chip is essentially the same as the
65 ------------------
67 Voltages are sampled by an 8-bit ADC with a LSB of 8 mV. The supported
84 in1 VIN1 VTT1.2V 10K - 1.00 1.20 V
[all …]
Dpc87427.rst10 Addresses scanned: none, address read from Super I/O config space
21 -----------
23 The National Semiconductor Super I/O chip includes complete hardware
36 --------------
38 Fan rotation speeds are reported as 14-bit values from a gated clock
41 An alarm is triggered if the rotation speed drops below a programmable
42 limit. Another alarm is triggered if the speed is too low to be measured
46 Fan Speed Control
47 -----------------
49 Fan speed can be controlled by PWM outputs. There are 4 possible modes:
[all …]
Dpc87360.rst10 Addresses scanned: none, address read from Super I/O config space
22 -----------------
27 - 0: None
28 - **1**: Forcibly enable internal voltage and temperature channels,
30 - 2: Forcibly enable all voltage and temperature channels, except in9
31 - 3: Forcibly enable all voltage and temperature channels, including in9
42 -----------
44 The National Semiconductor PC87360 Super I/O chip contains monitoring and
48 The National Semiconductor PC87365 and PC87366 Super I/O chips are complete
56 PC87360 - 2 2 - 0xE1
[all …]
/kernel/linux/linux-4.19/Documentation/hwmon/
Dnct677513 Addresses scanned: ISA address retrieved from Super I/O registers
15 * Nuvoton NCT5572D/NCT6771F/NCT6772F/NCT6775F/W83677HG-I
17 Addresses scanned: ISA address retrieved from Super I/O registers
21 Addresses scanned: ISA address retrieved from Super I/O registers
25 Addresses scanned: ISA address retrieved from Super I/O registers
29 Addresses scanned: ISA address retrieved from Super I/O registers
33 Addresses scanned: ISA address retrieved from Super I/O registers
37 Addresses scanned: ISA address retrieved from Super I/O registers
41 Addresses scanned: ISA address retrieved from Super I/O registers
45 Addresses scanned: ISA address retrieved from Super I/O registers
[all …]
Df71882fg7 Addresses scanned: none, address read from Super I/O config space
11 Addresses scanned: none, address read from Super I/O config space
15 Addresses scanned: none, address read from Super I/O config space
19 Addresses scanned: none, address read from Super I/O config space
23 Addresses scanned: none, address read from Super I/O config space
27 Addresses scanned: none, address read from Super I/O config space
31 Addresses scanned: none, address read from Super I/O config space
35 Addresses scanned: none, address read from Super I/O config space
39 Addresses scanned: none, address read from Super I/O config space
43 Addresses scanned: none, address read from Super I/O config space
[all …]
Dit877 Addresses scanned: from Super I/O config space (8 I/O ports)
11 Addresses scanned: from Super I/O config space (8 I/O ports)
14 Addresses scanned: from Super I/O config space (8 I/O ports)
18 Addresses scanned: from Super I/O config space (8 I/O ports)
22 Addresses scanned: from Super I/O config space (8 I/O ports)
26 Addresses scanned: from Super I/O config space (8 I/O ports)
30 Addresses scanned: from Super I/O config space (8 I/O ports)
34 Addresses scanned: from Super I/O config space (8 I/O ports)
38 Addresses scanned: from Super I/O config space (8 I/O ports)
42 Addresses scanned: from Super I/O config space (8 I/O ports)
[all …]
Dw83627ehf7 Addresses scanned: ISA address retrieved from Super I/O registers
11 Addresses scanned: ISA address retrieved from Super I/O registers
13 * Winbond W83627DHG-P
15 Addresses scanned: ISA address retrieved from Super I/O registers
19 Addresses scanned: ISA address retrieved from Super I/O registers
23 Addresses scanned: ISA address retrieved from Super I/O registers
25 * Winbond W83667HG-B
27 Addresses scanned: ISA address retrieved from Super I/O registers
29 * Nuvoton NCT6775F/W83667HG-I
31 Addresses scanned: ISA address retrieved from Super I/O registers
[all …]
Df71805f7 Addresses scanned: none, address read from Super I/O config space
11 Addresses scanned: none, address read from Super I/O config space
15 Addresses scanned: none, address read from Super I/O config space
32 -----------
34 The Fintek F71805F/FG Super I/O chip includes complete hardware monitoring
41 The Fintek F71872F/FG Super I/O chip is almost the same, with two
45 The Fintek F71806F/FG Super-I/O chip is essentially the same as the
53 ------------------
55 Voltages are sampled by an 8-bit ADC with a LSB of 8 mV. The supported
71 in1 VIN1 VTT1.2V 10K - 1.00 1.20 V
[all …]
Dpc873607 Addresses scanned: none, address read from Super I/O config space
17 -----------------
35 -----------
37 The National Semiconductor PC87360 Super I/O chip contains monitoring and
41 The National Semiconductor PC87365 and PC87366 Super I/O chips are complete
48 PC87360 - 2 2 - 0xE1
49 PC87363 - 2 2 - 0xE8
50 PC87364 - 3 3 - 0xE4
52 PC87366 11 3 3 3-4 0xE9
55 standard Super I/O addresses is used (0x2E/0x2F or 0x4E/0x4F)
[all …]
Dpc874277 Addresses scanned: none, address read from Super I/O config space
17 -----------
19 The National Semiconductor Super I/O chip includes complete hardware
32 --------------
34 Fan rotation speeds are reported as 14-bit values from a gated clock
37 An alarm is triggered if the rotation speed drops below a programmable
38 limit. Another alarm is triggered if the speed is too low to be measured
42 Fan Speed Control
43 -----------------
45 Fan speed can be controlled by PWM outputs. There are 4 possible modes:
[all …]
/kernel/linux/linux-5.10/drivers/usb/gadget/function/
Du_uvc.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Copyright (c) 2013-2014 Samsung Electronics Co., Ltd.
32 * Control descriptors array pointers for full-/high-speed and
33 * super-speed. They point by default to the uvc_fs_control_cls and
41 * Streaming descriptors array pointers for full-speed, high-speed and
42 * super-speed. They will point to the uvc_[fhs]s_streaming_cls arrays
43 * for configfs-based gadgets. Legacy gadgets must initialize them in
50 /* Default control descriptors for configfs-based gadgets. */
57 * Control descriptors pointers arrays for full-/high-speed and
58 * super-speed. The first element is a configurable control header
[all …]
/kernel/linux/linux-4.19/drivers/usb/gadget/function/
Du_uvc.h1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (c) 2013-2014 Samsung Electronics Co., Ltd.
29 * Control descriptors array pointers for full-/high-speed and
30 * super-speed. They point by default to the uvc_fs_control_cls and
38 * Streaming descriptors array pointers for full-speed, high-speed and
39 * super-speed. They will point to the uvc_[fhs]s_streaming_cls arrays
40 * for configfs-based gadgets. Legacy gadgets must initialize them in
47 /* Default control descriptors for configfs-based gadgets. */
54 * Control descriptors pointers arrays for full-/high-speed and
55 * super-speed. The first element is a configurable control header
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Dgeneric.txt4 - maximum-speed: tells USB controllers we want to work up to a certain
5 speed. Valid arguments are "super-speed-plus",
6 "super-speed", "high-speed", "full-speed" and
7 "low-speed". In case this isn't passed via DT, USB
10 - dr_mode: tells Dual-Role USB controllers that we want to work on a
15 - phy_type: tells USB controllers that we want to configure the core to support
16 a UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is
20 - otg-rev: tells usb driver the release number of the OTG and EH supplement
22 in binary-coded decimal (i.e. 2.0 is 0200H). This
24 is enabled, if ADP is required, otg-rev should be
[all …]
Dcdns,usb3.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence USBSS-DRD controller bindings
10 - Pawel Laszczak <pawell@cadence.com>
18 - description: OTG controller registers
19 - description: XHCI Host controller registers
20 - description: DEVICE controller registers
22 reg-names:
24 - const: otg
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dsocionext,uniphier-usb3ss-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro4-usb3-ssphy
22 - socionext,uniphier-pro5-usb3-ssphy
[all …]
Dnvidia,tegra124-xusb-padctl.txt11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
34 --------------------
35 - compatible: Must be:
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/usb/
Dgeneric.txt4 - maximum-speed: tells USB controllers we want to work up to a certain
5 speed. Valid arguments are "super-speed", "high-speed",
6 "full-speed" and "low-speed". In case this isn't passed
9 - dr_mode: tells Dual-Role USB controllers that we want to work on a
14 - phy_type: tells USB controllers that we want to configure the core to support
15 a UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is
19 - otg-rev: tells usb driver the release number of the OTG and EH supplement
21 in binary-coded decimal (i.e. 2.0 is 0200H). This
23 is enabled, if ADP is required, otg-rev should be
25 - companion: phandle of a companion
[all …]
/kernel/linux/linux-5.10/drivers/phy/qualcomm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
26 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
58 controllers on Qualcomm chips. This driver supports the high-speed
65 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
68 Support for the USB high-speed ULPI compliant phy on Qualcomm
76 Enable support for the USB high-speed SNPS Femto phy on Qualcomm
89 tristate "Qualcomm 28nm High-Speed PHY"
91 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
95 High-Speed PHY driver. This driver supports the Hi-Speed PHY which
100 tristate "Qualcomm USB Super-Speed PHY driver"
[all …]
/kernel/linux/linux-5.10/Documentation/driver-api/usb/
Dusb3-debug-port.rst19 3) have a USB 3.0 super-speed A-to-A debugging cable.
30 super-speed port). The debug device is fully compliant with
32 performance full-duplex serial link between the debug target
41 Other uses include simpler, lockless logging instead of a full-
58 "usbcore.autosuspend=-1"
63 should be a USB 3.0 super-speed A-to-A debugging cable.
74 # tail -f /var/log/kern.log
75 [ 1815.983374] usb 4-3: new SuperSpeed USB device number 4 using xhci_hcd
76 [ 1815.999595] usb 4-3: LPM exit latency is zeroed, disabling LPM.
77 [ 1815.999899] usb 4-3: New USB device found, idVendor=1d6b, idProduct=0004
[all …]
/kernel/linux/linux-4.19/Documentation/driver-api/usb/
Dusb3-debug-port.rst19 3) have a USB 3.0 super-speed A-to-A debugging cable.
30 super-speed port). The debug device is fully compliant with
32 performance full-duplex serial link between the debug target
41 Other uses include simpler, lockless logging instead of a full-
58 "usbcore.autosuspend=-1"
63 should be a USB 3.0 super-speed A-to-A debugging cable.
74 # tail -f /var/log/kern.log
75 [ 1815.983374] usb 4-3: new SuperSpeed USB device number 4 using xhci_hcd
76 [ 1815.999595] usb 4-3: LPM exit latency is zeroed, disabling LPM.
77 [ 1815.999899] usb 4-3: New USB device found, idVendor=1d6b, idProduct=0004
[all …]
/kernel/linux/linux-5.10/drivers/usb/gadget/udc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
7 # NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !!
9 # - Host systems (like PCs) need CONFIG_USB (with "A" jacks).
10 # - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks).
11 # - Some systems have both kinds of controllers.
13 # With help from a special transceiver and a "Mini-AB" jack, systems with
14 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
22 # - integrated/SOC controllers first
23 # - licensed IP used in both SOC and discrete versions
24 # - discrete ones (including all PCI-only controllers)
[all …]

1234567891011