Home
last modified time | relevance | path

Searched +full:ahb +full:- +full:addr +full:- +full:masks (Results 1 – 10 of 10) sorted by relevance

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/
Dst,stm32-mdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a five-cell specifier for each channel:
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
30 -bit 8-9: Source increment offset size
32 0x1: half-word (16bit)
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/dma/
Dstm32-mdma.txt3 The STM32 MDMA is a general-purpose direct memory access controller capable of
7 - compatible: Should be "st,stm32h7-mdma"
8 - reg: Should contain MDMA registers location and length. This should include
9 all of the per-channel registers.
10 - interrupts: Should contain the MDMA interrupt.
11 - clocks: Should contain the input clock of the DMA instance.
12 - resets: Reference to a reset controller asserting the DMA controller.
13 - #dma-cells : Must be <5>. See DMA client paragraph for more details.
16 - dma-channels: Number of DMA channels supported by the controller.
17 - dma-requests: Number of DMA request signals supported by the controller.
[all …]
/kernel/linux/linux-4.19/drivers/misc/
Daspeed-lpc-ctrl.c20 #include <linux/aspeed-lpc-ctrl.h>
22 #define DEVICE_NAME "aspeed-lpc-ctrl"
43 return container_of(file->private_data, struct aspeed_lpc_ctrl, in file_aspeed_lpc_ctrl()
50 unsigned long vsize = vma->vm_end - vma->vm_start; in aspeed_lpc_ctrl_mmap()
51 pgprot_t prot = vma->vm_page_prot; in aspeed_lpc_ctrl_mmap()
53 if (vma->vm_pgoff + vsize > lpc_ctrl->mem_base + lpc_ctrl->mem_size) in aspeed_lpc_ctrl_mmap()
54 return -EINVAL; in aspeed_lpc_ctrl_mmap()
56 /* ast2400/2500 AHB accesses are not cache coherent */ in aspeed_lpc_ctrl_mmap()
59 if (remap_pfn_range(vma, vma->vm_start, in aspeed_lpc_ctrl_mmap()
60 (lpc_ctrl->mem_base >> PAGE_SHIFT) + vma->vm_pgoff, in aspeed_lpc_ctrl_mmap()
[all …]
/kernel/linux/linux-5.10/drivers/soc/aspeed/
Daspeed-lpc-ctrl.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <linux/aspeed-lpc-ctrl.h>
18 #define DEVICE_NAME "aspeed-lpc-ctrl"
39 return container_of(file->private_data, struct aspeed_lpc_ctrl, in file_aspeed_lpc_ctrl()
46 unsigned long vsize = vma->vm_end - vma->vm_start; in aspeed_lpc_ctrl_mmap()
47 pgprot_t prot = vma->vm_page_prot; in aspeed_lpc_ctrl_mmap()
49 if (vma->vm_pgoff + vma_pages(vma) > lpc_ctrl->mem_size >> PAGE_SHIFT) in aspeed_lpc_ctrl_mmap()
50 return -EINVAL; in aspeed_lpc_ctrl_mmap()
52 /* ast2400/2500 AHB accesses are not cache coherent */ in aspeed_lpc_ctrl_mmap()
55 if (remap_pfn_range(vma, vma->vm_start, in aspeed_lpc_ctrl_mmap()
[all …]
/kernel/linux/linux-4.19/drivers/usb/gadget/udc/aspeed-vhub/
Dvhub.h1 /* SPDX-License-Identifier: GPL-2.0+ */
87 /* EP ACK/NACK IRQ masks */
112 * per-device register definitions *
151 * per-endpoint register definitions *
213 #define AST_VHUB_NUM_GEN_EPs 15 /* Generic non-0 EPs */
233 /* A transfer request, either core-originated or internal */
242 * Desc number of the final packet or -1. For non-desc
395 /* Per-port info */
416 std_req_stall = -1, /* Stall requested */
423 #define UDCVDBG(u, fmt...) dev_dbg(&(u)->pdev->dev, fmt)
[all …]
/kernel/linux/linux-5.10/drivers/usb/gadget/udc/aspeed-vhub/
Dvhub.h1 /* SPDX-License-Identifier: GPL-2.0+ */
83 /* EP ACK/NACK IRQ masks */
107 * per-device register definitions *
146 * per-endpoint register definitions *
213 #define AST_VHUB_NUM_GEN_EPs 15 /* Generic non-0 EPs */
233 /* A transfer request, either core-originated or internal */
242 * Desc number of the final packet or -1. For non-desc
315 /* Index in global pool (zero-based) */
345 /* Device index (zero-based) and name string */
402 /* Per-port info */
[all …]
/kernel/linux/linux-5.10/drivers/dma/
Dstm32-mdma.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
10 * Inspired by stm32-dma.c and dma-jz4780.c
16 #include <linux/dma-mapping.h>
33 #include "virt-dma.h"
36 #define STM32_MDMA_SHIFT(n) (ffs(n) - 1)
286 return container_of(chan->vchan.chan.device, struct stm32_mdma_device, in stm32_mdma_get_dev()
302 return &chan->vchan.chan.dev->device; in chan2dev()
307 return mdma_dev->ddev.dev; in mdma2dev()
312 return readl_relaxed(dmadev->base + reg); in stm32_mdma_read()
[all …]
Damba-pl08x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (c) 2010 ST-Ericsson SA
27 * - CH_CONFIG register at different offset,
28 * - separate CH_CONTROL2 register for transfer size,
29 * - bigger maximum transfer size,
30 * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word,
31 * - no support for peripheral flow control.
45 * (Bursts are irrelevant for mem to mem transfers - there are no burst
46 * signals, the DMA controller will simply facilitate its AHB master.)
51 * - DMAC flow control: the transfer size defines the number of transfers
[all …]
/kernel/linux/linux-4.19/drivers/dma/
Dstm32-mdma.c5 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
20 * Inspired by stm32-dma.c and dma-jz4780.c
27 #include <linux/dma-mapping.h>
43 #include "virt-dma.h"
46 #define STM32_MDMA_SHIFT(n) (ffs(n) - 1)
297 return container_of(chan->vchan.chan.device, struct stm32_mdma_device, in stm32_mdma_get_dev()
313 return &chan->vchan.chan.dev->device; in chan2dev()
318 return mdma_dev->ddev.dev; in mdma2dev()
323 return readl_relaxed(dmadev->base + reg); in stm32_mdma_read()
328 writel_relaxed(val, dmadev->base + reg); in stm32_mdma_write()
[all …]
Damba-pl08x.c3 * Copyright (c) 2010 ST-Ericsson SA
39 * - CH_CONFIG register at different offset,
40 * - separate CH_CONTROL2 register for transfer size,
41 * - bigger maximum transfer size,
42 * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word,
43 * - no support for peripheral flow control.
57 * (Bursts are irrelevant for mem to mem transfers - there are no burst
58 * signals, the DMA controller will simply facilitate its AHB master.)
63 * - DMAC flow control: the transfer size defines the number of transfers
70 * - Peripheral flow control: the transfer size is ignored (and should be
[all …]