| /kernel/linux/linux-4.19/arch/ia64/sn/kernel/sn2/ |
| D | cache.c | 14 * sn_flush_all_caches - flush a range of address from all caches (incl. L4)
18 * Flush a range of addresses from all caches including L4.
21 * from all caches.
34 * The last call may have returned before the caches in sn_flush_all_caches()
|
| /kernel/linux/linux-4.19/Documentation/block/ |
| D | writeback_cache_control.txt | 9 write back caches. That means the devices signal I/O completion to the
60 devices with volatile caches need to implement the support for these
67 For devices that do not support volatile write caches there is no driver
70 requests that have a payload. For devices with volatile write caches the
71 driver needs to tell the block layer that it supports flushing caches by
|
| /kernel/linux/linux-5.10/Documentation/block/ |
| D | writeback_cache_control.rst | 9 write back caches. That means the devices signal I/O completion to the
60 devices with volatile caches need to implement the support for these
67 For devices that do not support volatile write caches there is no driver
70 requests that have a payload. For devices with volatile write caches the
71 driver needs to tell the block layer that it supports flushing caches by
|
| /kernel/linux/linux-4.19/arch/c6x/platforms/ |
| D | cache.c | 17 * Internal Memory Control Registers for caches
110 * L1 & L2 caches generic functions
211 * L1 caches management
215 * Disable L1 caches
229 * Enable L1 caches
285 * L2 caches management
425 * L1 and L2 caches configuration
442 /* Set L2 caches on the the whole L2 SRAM memory */ in c6x_cache_init()
|
| /kernel/linux/linux-5.10/arch/sparc/include/asm/ |
| D | viking.h | 27 * and never caches them internally (or so states the docs). Therefore
38 * on chip split I/D caches of the GNU/Viking.
45 * caches will snoop regardless of whether they are enabled, this
46 * takes care of the case where the I or D or both caches are turned
58 * caches, they may be cached by the GNU/MXCC if present and enabled.
72 * caches during that cycle. If disabled, all stores operations
78 * These bits enable the on-cpu GNU/Viking split I/D caches. Note,
79 * as mentioned above, these caches will snoop the bus in GNU/MBUS
|
| /kernel/linux/linux-4.19/arch/sparc/include/asm/ |
| D | viking.h | 26 * and never caches them internally (or so states the docs). Therefore
37 * on chip split I/D caches of the GNU/Viking.
44 * caches will snoop regardless of whether they are enabled, this
45 * takes care of the case where the I or D or both caches are turned
57 * caches, they may be cached by the GNU/MXCC if present and enabled.
71 * caches during that cycle. If disabled, all stores operations
77 * These bits enable the on-cpu GNU/Viking split I/D caches. Note,
78 * as mentioned above, these caches will snoop the bus in GNU/MBUS
|
| /kernel/linux/linux-5.10/arch/c6x/platforms/ |
| D | cache.c | 14 * Internal Memory Control Registers for caches
107 * L1 & L2 caches generic functions
208 * L1 caches management
212 * Disable L1 caches
226 * Enable L1 caches
282 * L2 caches management
422 * L1 and L2 caches configuration
439 /* Set L2 caches on the the whole L2 SRAM memory */ in c6x_cache_init()
|
| /kernel/linux/linux-4.19/mm/ |
| D | slab.h | 30 struct list_head list; /* List of all slab caches on the system */
55 * have the problem that the structures used for managing slab caches are
56 * allocated from slab caches themselves.
62 UP, /* Slab caches usable but not all extras yet */
71 /* The list of all slab caches on the system */
209 /* List of all root caches. */
214 * Iterate over all memcg caches of the given root cache. The caller must hold
233 * We use suffixes to the name in memcg because we can't have caches
245 * Note, we protect with RCU only the memcg_caches array, not per-memcg caches.
302 /* If !memcg, all caches are root. */
|
| /kernel/linux/linux-4.19/arch/openrisc/ |
| D | Kconfig | 88 bool "Have write through data caches"
91 Select this if your implementation features write through data caches.
93 caches at relevant times. Most OpenRISC implementations support write-
94 through data caches.
|
| /kernel/linux/linux-5.10/arch/openrisc/ |
| D | Kconfig | 84 bool "Have write through data caches"
87 Select this if your implementation features write through data caches.
89 caches at relevant times. Most OpenRISC implementations support write-
90 through data caches.
|
| /kernel/linux/linux-5.10/include/linux/ |
| D | kvm_types.h | 65 * Memory caches are used to preallocate memory ahead of various MMU flows,
68 * holding MMU locks. Note, these caches act more like prefetch buffers than
69 * classical caches, i.e. objects are not returned to the cache on being freed.
|
| /kernel/linux/linux-4.19/Documentation/filesystems/nfs/ |
| D | rpc-cache.txt | 5 CACHES
8 a wide variety of values to be caches.
10 There are a number of caches that are similar in structure though
12 of common code for managing these caches.
14 Examples of caches that are likely to be needed are:
92 includes it on a list of caches that will be regularly
|
| /kernel/linux/linux-5.10/Documentation/filesystems/nfs/ |
| D | rpc-cache.rst | 9 Caches subtitle
13 a wide variety of values to be caches.
15 There are a number of caches that are similar in structure though
17 of common code for managing these caches.
19 Examples of caches that are likely to be needed are:
105 includes it on a list of caches that will be regularly
|
| /kernel/linux/linux-4.19/include/linux/ |
| D | slab.h | 158 * Please use this macro to create slab caches. Simply specify the
198 * Some archs want to perform DMA into kmalloc caches and need a guaranteed
480 * Should only be used for kmalloc() caches. Otherwise, use a
566 * This is the main placeholder for memcg-related information in kmem caches.
567 * Both the root cache and the child caches will have it. For the root cache,
573 * Root and child caches hold different metadata.
575 * @root_cache: Common to root and child caches. NULL for root, pointer to
578 * The following fields are specific to root caches.
580 * @memcg_caches: kmemcg ID indexed table of child caches. This table is
586 * @children: List of all child caches. While the child caches are also
[all …]
|
| /kernel/linux/linux-5.10/arch/arm64/kernel/ |
| D | cacheinfo.c | 57 /* Separate instruction and data caches */ in init_cache_level()
68 * some external caches not specified in CLIDR_EL1 in init_cache_level()
70 * only unified external caches are considered here in init_cache_level()
|
| /kernel/linux/linux-5.10/arch/mips/kernel/ |
| D | bmips_5xxx_init.S | 300 * Description: Enable I and D caches, initialize I and D-caches, also set
323 * Description: Enable I and D caches, and initialize I and D-caches
344 /* Enable Caches before Clearing. If the caches are disabled
715 * Description: Enable I and D caches, and initialize I and D-caches
|
| /kernel/linux/linux-4.19/arch/mips/kernel/ |
| D | bmips_5xxx_init.S | 300 * Description: Enable I and D caches, initialize I and D-caches, also set
323 * Description: Enable I and D caches, and initialize I and D-caches
344 /* Enable Caches before Clearing. If the caches are disabled
721 * Description: Enable I and D caches, and initialize I and D-caches
|
| /kernel/linux/linux-5.10/arch/mips/include/asm/ |
| D | io.h | 495 * The caches on some architectures aren't dma-coherent and have need to
499 * - dma_cache_wback_inv(start, size) makes caches and coherent by
500 * writing the content of the caches back to memory, if necessary.
501 * The function also invalidates the affected part of the caches as
503 * - dma_cache_wback(start, size) makes caches and coherent by
504 * writing the content of the caches back to memory, if necessary.
505 * The function also invalidates the affected part of the caches as
508 * caches. Dirty lines of the caches may be written back or simply
|
| /kernel/linux/linux-4.19/arch/mips/include/asm/ |
| D | io.h | 243 * the PCI bus. Note that there are other caches and buffers on many
576 * The caches on some architectures aren't dma-coherent and have need to
580 * - dma_cache_wback_inv(start, size) makes caches and coherent by
581 * writing the content of the caches back to memory, if necessary.
582 * The function also invalidates the affected part of the caches as
584 * - dma_cache_wback(start, size) makes caches and coherent by
585 * writing the content of the caches back to memory, if necessary.
586 * The function also invalidates the affected part of the caches as
589 * caches. Dirty lines of the caches may be written back or simply
|
| /kernel/linux/linux-4.19/arch/openrisc/include/asm/ |
| D | cacheflush.h | 25 * and instruction caches. SMP needs a little extra work, since we need
46 * Synchronizes caches. Whenever a cpu writes executable code to memory, this
71 * indexed or tagged caches. So we can use the default here.
|
| /kernel/linux/linux-4.19/arch/arm64/kernel/ |
| D | cacheinfo.c | 59 /* Separate instruction and data caches */ in __init_cache_level()
70 * some external caches not specified in CLIDR_EL1 in __init_cache_level()
72 * only unified external caches are considered here in __init_cache_level()
|
| /kernel/linux/linux-5.10/tools/cgroup/ |
| D | memcg_slabinfo.py | 184 caches = {}
203 caches[addr] = cache
215 for addr in caches:
217 cache_show(caches[addr], cfg, stats[addr])
|
| /kernel/linux/linux-5.10/arch/mips/mm/ |
| D | c-r4k.c | 76 * separate caches). in r4k_op_needs_ipi()
499 * These caches are inclusive caches, that is, if something in local_r4k___flush_cache_all()
501 * in one of the primary caches. in local_r4k___flush_cache_all()
580 * whole caches when vma is executable.
620 * only flush the primary caches but R1x000 behave sane ... in local_r4k_flush_cache_mm()
622 * caches, so we can bail out early. in local_r4k_flush_cache_mm()
881 * Either no secondary cache or the available caches don't have the in r4k_dma_cache_wback_inv()
882 * subset property so we have to flush the primary caches in r4k_dma_cache_wback_inv()
985 * Aliases only affect the primary caches so don't bother with in local_r4k_flush_kernel_vmap_range_index()
986 * S-caches or T-caches. in local_r4k_flush_kernel_vmap_range_index()
[all …]
|
| /kernel/linux/linux-4.19/arch/powerpc/boot/ |
| D | gamecube-head.S | 19 * - if the data and instruction caches are enabled or not
22 * We enable the caches if not already enabled, enable the MMU with an
80 /* enable and invalidate the caches if not already enabled */
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/ |
| D | i915_globals.c | 120 * Defer shrinking the global slab caches (and other work) until in i915_globals_park()
123 * by us shrinking the caches the same time as they are trying to in i915_globals_park()
126 * to be longer until we need the caches again. in i915_globals_park()
|