| /kernel/linux/linux-4.19/include/linux/ |
| D | clk.h | 2 * linux/include/linux/clk.h
6 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
20 struct clk;
25 * DOC: clk notifier callback types
27 * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
35 * the clk will be called with ABORT_RATE_CHANGE. Callbacks must
38 * POST_RATE_CHANGE - called after the clk rate change has successfully
47 * struct clk_notifier - associate a clk with a notifier
48 * @clk: struct clk * to associate the notifier with
49 * @notifier_head: a blocking_notifier_head for this clk
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| /kernel/linux/linux-5.10/include/linux/ |
| D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/include/linux/clk.h
7 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
17 struct clk;
22 * DOC: clk notifier callback types
24 * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
32 * the clk will be called with ABORT_RATE_CHANGE. Callbacks must
35 * POST_RATE_CHANGE - called after the clk rate change has successfully
44 * struct clk_notifier - associate a clk with a notifier
45 * @clk: struct clk * to associate the notifier with
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| /kernel/linux/linux-5.10/drivers/clk/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
20 Select this option when the clock API in <linux/clk.h> is implemented
23 'struct clk'.
34 clk, useful across many platforms, as well as an
35 implementation of the clock API in include/linux/clk.h.
36 Architectures utilizing the common struct clk should select
48 source "drivers/clk/versatile/Kconfig"
76 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
86 multi-function device has one fixed-rate oscillator, clocked
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| /kernel/linux/linux-4.19/drivers/clk/ |
| D | Kconfig | 15 ---help---
17 clk, useful across many platforms, as well as an
18 implementation of the clock API in include/linux/clk.h.
19 Architectures utilizing the common struct clk should select
28 ---help---
32 source "drivers/clk/versatile/Kconfig"
37 ---help---
44 ---help---
57 ---help---
59 multi-function devices have two fixed-rate oscillators,
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ |
| D | at91-clock.txt | 1 Device Tree Clock bindings for arch-at91
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "atmel,at91sam9x5-sckc" or
10 "atmel,sama5d4-sckc":
14 "atmel,at91sam9x5-clk-slow-osc":
17 "atmel,at91sam9x5-clk-slow-rc-osc":
20 "atmel,<chip>-pmc":
28 "atmel,at91sam9x5-clk-slow" (under sckc node)
30 "atmel,at91sam9260-clk-slow" (under pmc node):
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| /kernel/linux/linux-4.19/drivers/cpufreq/ |
| D | spear-cpufreq.c | 2 * drivers/cpufreq/spear-cpufreq.c
16 #include <linux/clk.h>
28 struct clk *clk; member
34 static struct clk *spear1340_cpu_get_possible_parent(unsigned long newfreq) in spear1340_cpu_get_possible_parent()
36 struct clk *sys_pclk; in spear1340_cpu_get_possible_parent()
39 * In SPEAr1340, cpu clk's parent sys clk can take input from in spear1340_cpu_get_possible_parent()
50 * As sys clk can have multiple source with their own range in spear1340_cpu_get_possible_parent()
60 return ERR_PTR(-EINVAL); in spear1340_cpu_get_possible_parent()
72 * access a source clock (clk) which might not be ancestor of cpu at present.
73 * Hence in SPEAr1340 we would operate on source clock directly before switching
[all …]
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| /kernel/linux/linux-5.10/drivers/cpufreq/ |
| D | spear-cpufreq.c | 2 * drivers/cpufreq/spear-cpufreq.c
16 #include <linux/clk.h>
28 struct clk *clk; member
34 static struct clk *spear1340_cpu_get_possible_parent(unsigned long newfreq) in spear1340_cpu_get_possible_parent()
36 struct clk *sys_pclk; in spear1340_cpu_get_possible_parent()
39 * In SPEAr1340, cpu clk's parent sys clk can take input from in spear1340_cpu_get_possible_parent()
50 * As sys clk can have multiple source with their own range in spear1340_cpu_get_possible_parent()
60 return ERR_PTR(-EINVAL); in spear1340_cpu_get_possible_parent()
72 * access a source clock (clk) which might not be ancestor of cpu at present.
73 * Hence in SPEAr1340 we would operate on source clock directly before switching
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/tegra/ |
| D | clk-super.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
13 #include "clk.h"
28 #define super_state_to_src_shift(m, s) ((m->width * s))
29 #define super_state_to_src_mask(m) (((1 << m->width) - 1))
38 u8 source, shift; in clk_super_get_parent() local
40 val = readl_relaxed(mux->reg); in clk_super_get_parent()
50 source = (val >> shift) & super_state_to_src_mask(mux); in clk_super_get_parent()
54 * PLLX/2 is the input source to CCLKLP. in clk_super_get_parent()
56 if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) && in clk_super_get_parent()
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| D | clk-tegra210-emc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/clk/tegra.h>
15 #include "clk.h"
37 struct clk *parents[8];
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate()
72 * parent before the ->set_rate() call. in tegra210_clk_emc_recalc_rate()
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| /kernel/linux/linux-4.19/drivers/clk/tegra/ |
| D | clk-super.c | 22 #include <linux/clk-provider.h>
24 #include "clk.h"
39 #define super_state_to_src_shift(m, s) ((m->width * s))
40 #define super_state_to_src_mask(m) (((1 << m->width) - 1))
46 u8 source, shift; in clk_super_get_parent() local
48 val = readl_relaxed(mux->reg); in clk_super_get_parent()
58 source = (val >> shift) & super_state_to_src_mask(mux); in clk_super_get_parent()
62 * PLLX/2 is the input source to CCLKLP. in clk_super_get_parent()
64 if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) && in clk_super_get_parent()
65 (source == mux->pllx_index)) in clk_super_get_parent()
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| /kernel/linux/linux-4.19/drivers/clocksource/ |
| D | timer-nps.c | 7 * COPYING in the main directory of this source tree, or the
10 * Redistribution and use in source and binary forms, with or
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
36 #include <linux/clk.h>
51 struct clk **clk) in nps_get_timer_clk() argument
55 *clk = of_clk_get(node, 0); in nps_get_timer_clk()
56 ret = PTR_ERR_OR_ZERO(*clk); in nps_get_timer_clk()
58 pr_err("timer missing clk\n"); in nps_get_timer_clk()
62 ret = clk_prepare_enable(*clk); in nps_get_timer_clk()
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| D | fsl_ftm_timer.c | 12 #include <linux/clk.h>
49 if (priv->big_endian) in ftm_readl()
57 if (priv->big_endian) in ftm_writel()
67 /* select and enable counter clock source */ in ftm_counter_enable()
70 val |= priv->ps | FTM_SC_CLK(1); in ftm_counter_enable()
78 /* disable counter clock source */ in ftm_counter_disable()
123 return ftm_readl(priv->clksrc_base + FTM_CNT); in ftm_read_sched_clock()
134 * a, the counter source clock is diabled. in ftm_set_next_event()
136 ftm_counter_disable(priv->clkevt_base); in ftm_set_next_event()
139 ftm_reset_counter(priv->clkevt_base); in ftm_set_next_event()
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| D | cadence_ttc_timer.c | 4 * Copyright (C) 2011-2013 Xilinx
18 #include <linux/clk.h>
28 * This driver configures the 2 16/32-bit count-up timers as follows:
31 * T2: Timer 2, clockevent source for hrtimers
35 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
39 * obtained from device tree. The pre-scaler of 32 is used.
55 #define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */
60 * Setup the timers to use pre-scaling, using a fixed value for now that will
65 #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
72 * struct ttc_timer - This definition defines local timer structure
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| /kernel/linux/linux-5.10/drivers/clocksource/ |
| D | timer-nps.c | 7 * COPYING in the main directory of this source tree, or the
10 * Redistribution and use in source and binary forms, with or
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
36 #include <linux/clk.h>
51 struct clk **clk) in nps_get_timer_clk() argument
55 *clk = of_clk_get(node, 0); in nps_get_timer_clk()
56 ret = PTR_ERR_OR_ZERO(*clk); in nps_get_timer_clk()
58 pr_err("timer missing clk\n"); in nps_get_timer_clk()
62 ret = clk_prepare_enable(*clk); in nps_get_timer_clk()
[all …]
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| D | timer-fsl-ftm.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
34 if (priv->big_endian) in ftm_readl()
42 if (priv->big_endian) in ftm_writel()
52 /* select and enable counter clock source */ in ftm_counter_enable()
55 val |= priv->ps | FTM_SC_CLK(1); in ftm_counter_enable()
63 /* disable counter clock source */ in ftm_counter_disable()
108 return ftm_readl(priv->clksrc_base + FTM_CNT); in ftm_read_sched_clock()
119 * a, the counter source clock is diabled. in ftm_set_next_event()
121 ftm_counter_disable(priv->clkevt_base); in ftm_set_next_event()
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| /kernel/linux/linux-5.10/drivers/net/can/mscan/ |
| D | mpc5xxx_can.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
19 #include <linux/clk.h>
36 { .compatible = "fsl,mpc5200-cdm", },
53 * (IP_CLK) can be selected as MSCAN clock source. According to in mpc52xx_can_get_clock()
64 freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); in mpc52xx_can_get_clock()
74 dev_err(&ofdev->dev, "can't get clock node!\n"); in mpc52xx_can_get_clock()
80 dev_err(&ofdev->dev, "can't map clock node!\n"); in mpc52xx_can_get_clock()
84 if (in_8(&cdm->ipb_clk_sel) & 0x1) in mpc52xx_can_get_clock()
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| /kernel/linux/linux-4.19/drivers/net/can/mscan/ |
| D | mpc5xxx_can.c | 4 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
6 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
30 #include <linux/clk.h>
47 { .compatible = "fsl,mpc5200-cdm", },
64 * (IP_CLK) can be selected as MSCAN clock source. According to in mpc52xx_can_get_clock()
75 freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); in mpc52xx_can_get_clock()
85 dev_err(&ofdev->dev, "can't get clock node!\n"); in mpc52xx_can_get_clock()
91 dev_err(&ofdev->dev, "can't map clock node!\n"); in mpc52xx_can_get_clock()
95 if (in_8(&cdm->ipb_clk_sel) & 0x1) in mpc52xx_can_get_clock()
97 val = in_be32(&cdm->rstcfg); in mpc52xx_can_get_clock()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/renesas/ |
| D | r9a06g032-clocks.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
24 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
37 uint32_t source : 8; /* source index + 1 (0 == none) */ member
46 /* For fixed-factor ones */
66 .source = 1 + R9A06G032_##_src, .name = _n, \
70 .source = 1 + R9A06G032_##_src, .name = _n, \
77 .source = 1 + R9A06G032_##_src, .name = _n, \
81 .source = 1 + R9A06G032_##_src, .name = _n, \
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| /kernel/linux/linux-4.19/drivers/clk/renesas/ |
| D | r9a06g032-clocks.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
33 uint32_t source : 8; /* source index + 1 (0 == none) */ member
42 /* For fixed-factor ones */
62 .source = 1 + R9A06G032_##_src, .name = _n, \
69 .source = 1 + R9A06G032_##_src, .name = _n, \
73 .source = 1 + R9A06G032_##_src, .name = _n, \
78 .source = 1 + R9A06G032_##_src, .name = _n, \
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| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | sdhci-s3c.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/mmc/host/sdhci-s3c.c
14 #include <linux/dma-mapping.h>
16 #include <linux/platform_data/mmc-sdhci-s3c.h>
18 #include <linux/clk.h>
104 * struct sdhci_s3c - S3C SDHCI instance
114 * @no_divider: No or non-standard internal clock divider.
124 struct clk *clk_io;
125 struct clk *clk_bus[MAX_BUS_CLK];
132 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
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| /kernel/linux/linux-4.19/drivers/mmc/host/ |
| D | sdhci-s3c.c | 1 /* linux/drivers/mmc/host/sdhci-s3c.c
17 #include <linux/dma-mapping.h>
19 #include <linux/platform_data/mmc-sdhci-s3c.h>
21 #include <linux/clk.h>
107 * struct sdhci_s3c - S3C SDHCI instance
125 struct clk *clk_io;
126 struct clk *clk_bus[MAX_BUS_CLK];
133 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
151 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
163 rate = ourhost->clk_rates[src]; in sdhci_s3c_get_max_clk()
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/sound/ |
| D | samsung-i2s.txt | 5 - compatible : should be one of the following.
6 - samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
7 - samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with
8 secondary fifo, s/w reset control and internal mux for root clk src.
9 - samsung,exynos5420-i2s: for 8/16/24bit multichannel(5.1) I2S for
11 or external dma, s/w reset control, internal mux for root clk src
14 - samsung,exynos7-i2s: with all the available features of exynos5 i2s,
16 with only external dma and more no.of root clk sampling frequencies.
17 - samsung,exynos7-i2s1: I2S1 on previous samsung platforms supports
21 - reg: physical base address of the controller and length of memory mapped
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/i2c/ |
| D | nvidia,tegra20-i2c.txt | 4 - compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or
5 "nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c".
6 For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be
7 "nvidia,<chip>-i2c", plus at least one of the above, where <chip> is
10 nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
14 "nvidia,tegra20-i2c-dvc".
15 nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support
16 master and slave mode of I2C communication. The i2c-tegra driver only
18 only compatible with "nvidia,tegra20-i2c".
19 nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is
[all …]
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| /kernel/linux/linux-5.10/drivers/pwm/ |
| D | pwm-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
18 * achieved is (max rate of source clock) / 256.
19 * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/ |
| D | nvidia,tegra20-i2c.txt | 4 - compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or
5 "nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c".
6 For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be
7 "nvidia,<chip>-i2c", plus at least one of the above, where <chip> is
10 nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
14 "nvidia,tegra20-i2c-dvc".
15 nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support
16 master and slave mode of I2C communication. The i2c-tegra driver only
18 only compatible with "nvidia,tegra20-i2c".
19 nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is
[all …]
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