1Device Tree Clock bindings for arch-at91 2 3This binding uses the common clock binding[1]. 4 5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 6 7Required properties: 8- compatible : shall be one of the following: 9 "atmel,at91sam9x5-sckc" or 10 "atmel,sama5d4-sckc": 11 at91 SCKC (Slow Clock Controller) 12 This node contains the slow clock definitions. 13 14 "atmel,at91sam9x5-clk-slow-osc": 15 at91 slow oscillator 16 17 "atmel,at91sam9x5-clk-slow-rc-osc": 18 at91 internal slow RC oscillator 19 20 "atmel,<chip>-pmc": 21 at91 PMC (Power Management Controller) 22 All at91 specific clocks (clocks defined below) must be child 23 node of the PMC node. 24 <chip> can be: at91rm9200, at91sam9260, at91sam9261, 25 at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9x5, 26 sama5d2, sama5d3 or sama5d4. 27 28 "atmel,at91sam9x5-clk-slow" (under sckc node) 29 or 30 "atmel,at91sam9260-clk-slow" (under pmc node): 31 at91 slow clk 32 33 "atmel,at91rm9200-clk-main-osc" 34 "atmel,at91sam9x5-clk-main-rc-osc" 35 at91 main clk sources 36 37 "atmel,at91sam9x5-clk-main" 38 "atmel,at91rm9200-clk-main": 39 at91 main clock 40 41 "atmel,at91rm9200-clk-master" or 42 "atmel,at91sam9x5-clk-master": 43 at91 master clock 44 45 "atmel,at91sam9x5-clk-peripheral" or 46 "atmel,at91rm9200-clk-peripheral": 47 at91 peripheral clocks 48 49 "atmel,at91rm9200-clk-pll" or 50 "atmel,at91sam9g45-clk-pll" or 51 "atmel,at91sam9g20-clk-pllb" or 52 "atmel,sama5d3-clk-pll": 53 at91 pll clocks 54 55 "atmel,at91sam9x5-clk-plldiv": 56 at91 plla divisor 57 58 "atmel,at91rm9200-clk-programmable" or 59 "atmel,at91sam9g45-clk-programmable" or 60 "atmel,at91sam9x5-clk-programmable": 61 at91 programmable clocks 62 63 "atmel,at91sam9x5-clk-smd": 64 at91 SMD (Soft Modem) clock 65 66 "atmel,at91rm9200-clk-system": 67 at91 system clocks 68 69 "atmel,at91rm9200-clk-usb" or 70 "atmel,at91sam9x5-clk-usb" or 71 "atmel,at91sam9n12-clk-usb": 72 at91 usb clock 73 74 "atmel,at91sam9x5-clk-utmi": 75 at91 utmi clock 76 77 "atmel,sama5d4-clk-h32mx": 78 at91 h32mx clock 79 80 "atmel,sama5d2-clk-generated": 81 at91 generated clock 82 83 "atmel,sama5d2-clk-audio-pll-frac": 84 at91 audio fractional pll 85 86 "atmel,sama5d2-clk-audio-pll-pad": 87 at91 audio pll CLK_AUDIO output pin 88 89 "atmel,sama5d2-clk-audio-pll-pmc" 90 at91 audio pll output on AUDIOPLLCLK that feeds the PMC 91 and can be used by peripheral clock or generic clock 92 93 "atmel,sama5d2-clk-i2s-mux" (under pmc node): 94 at91 I2S clock source selection 95 96Required properties for SCKC node: 97- reg : defines the IO memory reserved for the SCKC. 98- #size-cells : shall be 0 (reg is used to encode clk id). 99- #address-cells : shall be 1 (reg is used to encode clk id). 100 101 102For example: 103 sckc: sckc@fffffe50 { 104 compatible = "atmel,sama5d3-pmc"; 105 reg = <0xfffffe50 0x4> 106 #size-cells = <0>; 107 #address-cells = <1>; 108 109 /* put at91 slow clocks here */ 110 }; 111 112 113Required properties for internal slow RC oscillator: 114- #clock-cells : from common clock binding; shall be set to 0. 115- clock-frequency : define the internal RC oscillator frequency. 116 117Optional properties: 118- clock-accuracy : define the internal RC oscillator accuracy. 119 120For example: 121 slow_rc_osc: slow_rc_osc { 122 compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; 123 clock-frequency = <32768>; 124 clock-accuracy = <50000000>; 125 }; 126 127Required properties for slow oscillator: 128- #clock-cells : from common clock binding; shall be set to 0. 129- clocks : shall encode the main osc source clk sources (see atmel datasheet). 130 131Optional properties: 132- atmel,osc-bypass : boolean property. Set this when a clock signal is directly 133 provided on XIN. 134 135For example: 136 slow_osc: slow_osc { 137 compatible = "atmel,at91rm9200-clk-slow-osc"; 138 #clock-cells = <0>; 139 clocks = <&slow_xtal>; 140 }; 141 142Required properties for slow clock: 143- #clock-cells : from common clock binding; shall be set to 0. 144- clocks : shall encode the slow clk sources (see atmel datasheet). 145 146For example: 147 clk32k: slck { 148 compatible = "atmel,at91sam9x5-clk-slow"; 149 #clock-cells = <0>; 150 clocks = <&slow_rc_osc &slow_osc>; 151 }; 152 153Required properties for PMC node: 154- reg : defines the IO memory reserved for the PMC. 155- #size-cells : shall be 0 (reg is used to encode clk id). 156- #address-cells : shall be 1 (reg is used to encode clk id). 157- interrupts : shall be set to PMC interrupt line. 158- interrupt-controller : tell that the PMC is an interrupt controller. 159- #interrupt-cells : must be set to 1. The first cell encodes the interrupt id, 160 and reflect the bit position in the PMC_ER/DR/SR registers. 161 You can use the dt macros defined in dt-bindings/clock/at91.h. 162 0 (AT91_PMC_MOSCS) -> main oscillator ready 163 1 (AT91_PMC_LOCKA) -> PLL A ready 164 2 (AT91_PMC_LOCKB) -> PLL B ready 165 3 (AT91_PMC_MCKRDY) -> master clock ready 166 6 (AT91_PMC_LOCKU) -> UTMI PLL clock ready 167 8 .. 15 (AT91_PMC_PCKRDY(id)) -> programmable clock ready 168 16 (AT91_PMC_MOSCSELS) -> main oscillator selected 169 17 (AT91_PMC_MOSCRCS) -> RC main oscillator stabilized 170 18 (AT91_PMC_CFDEV) -> clock failure detected 171 172For example: 173 pmc: pmc@fffffc00 { 174 compatible = "atmel,sama5d3-pmc"; 175 interrupts = <1 4 7>; 176 interrupt-controller; 177 #interrupt-cells = <2>; 178 #size-cells = <0>; 179 #address-cells = <1>; 180 181 /* put at91 clocks here */ 182 }; 183 184Required properties for main clock internal RC oscillator: 185- interrupts : shall be set to "<0>". 186- clock-frequency : define the internal RC oscillator frequency. 187 188Optional properties: 189- clock-accuracy : define the internal RC oscillator accuracy. 190 191For example: 192 main_rc_osc: main_rc_osc { 193 compatible = "atmel,at91sam9x5-clk-main-rc-osc"; 194 interrupt-parent = <&pmc>; 195 interrupts = <0>; 196 clock-frequency = <12000000>; 197 clock-accuracy = <50000000>; 198 }; 199 200Required properties for main clock oscillator: 201- interrupts : shall be set to "<0>". 202- #clock-cells : from common clock binding; shall be set to 0. 203- clocks : shall encode the main osc source clk sources (see atmel datasheet). 204 205Optional properties: 206- atmel,osc-bypass : boolean property. Specified if a clock signal is provided 207 on XIN. 208 209 clock signal is directly provided on XIN pin. 210 211For example: 212 main_osc: main_osc { 213 compatible = "atmel,at91rm9200-clk-main-osc"; 214 interrupt-parent = <&pmc>; 215 interrupts = <0>; 216 #clock-cells = <0>; 217 clocks = <&main_xtal>; 218 }; 219 220Required properties for main clock: 221- interrupts : shall be set to "<0>". 222- #clock-cells : from common clock binding; shall be set to 0. 223- clocks : shall encode the main clk sources (see atmel datasheet). 224 225For example: 226 main: mainck { 227 compatible = "atmel,at91sam9x5-clk-main"; 228 interrupt-parent = <&pmc>; 229 interrupts = <0>; 230 #clock-cells = <0>; 231 clocks = <&main_rc_osc &main_osc>; 232 }; 233 234Required properties for master clock: 235- interrupts : shall be set to "<3>". 236- #clock-cells : from common clock binding; shall be set to 0. 237- clocks : shall be the master clock sources (see atmel datasheet) phandles. 238 e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>". 239- atmel,clk-output-range : minimum and maximum clock frequency (two u32 240 fields). 241 e.g. output = <0 133000000>; <=> 0 to 133MHz. 242- atmel,clk-divisors : master clock divisors table (four u32 fields). 243 0 <=> reserved value. 244 e.g. divisors = <1 2 4 6>; 245- atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the 246 PRES field as CLOCK_DIV3 (e.g sam9x5). 247 248For example: 249 mck: mck { 250 compatible = "atmel,at91rm9200-clk-master"; 251 interrupt-parent = <&pmc>; 252 interrupts = <3>; 253 #clock-cells = <0>; 254 atmel,clk-output-range = <0 133000000>; 255 atmel,clk-divisors = <1 2 4 0>; 256 }; 257 258Required properties for peripheral clocks: 259- #size-cells : shall be 0 (reg is used to encode clk id). 260- #address-cells : shall be 1 (reg is used to encode clk id). 261- clocks : shall be the master clock phandle. 262 e.g. clocks = <&mck>; 263- name: device tree node describing a specific peripheral clock. 264 * #clock-cells : from common clock binding; shall be set to 0. 265 * reg: peripheral id. See Atmel's datasheets to get a full 266 list of peripheral ids. 267 * atmel,clk-output-range : minimum and maximum clock frequency 268 (two u32 fields). Only valid on at91sam9x5-clk-peripheral 269 compatible IPs. 270 271For example: 272 periph: periphck { 273 compatible = "atmel,at91sam9x5-clk-peripheral"; 274 #size-cells = <0>; 275 #address-cells = <1>; 276 clocks = <&mck>; 277 278 ssc0_clk { 279 #clock-cells = <0>; 280 reg = <2>; 281 atmel,clk-output-range = <0 133000000>; 282 }; 283 284 usart0_clk { 285 #clock-cells = <0>; 286 reg = <3>; 287 atmel,clk-output-range = <0 66000000>; 288 }; 289 }; 290 291 292Required properties for pll clocks: 293- interrupts : shall be set to "<1>". 294- #clock-cells : from common clock binding; shall be set to 0. 295- clocks : shall be the main clock phandle. 296- reg : pll id. 297 0 -> PLL A 298 1 -> PLL B 299- atmel,clk-input-range : minimum and maximum source clock frequency (two u32 300 fields). 301 e.g. input = <1 32000000>; <=> 1 to 32MHz. 302- #atmel,pll-clk-output-range-cells : number of cells reserved for pll output 303 range description. Sould be set to 2, 3 304 or 4. 305 * 1st and 2nd cells represent the frequency range (min-max). 306 * 3rd cell is optional and represents the OUT field value for the given 307 range. 308 * 4th cell is optional and represents the ICPLL field (PLLICPR 309 register) 310- atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter 311 depending on #atmel,pll-output-range-cells 312 property value. 313 314For example: 315 plla: pllack { 316 compatible = "atmel,at91sam9g45-clk-pll"; 317 interrupt-parent = <&pmc>; 318 interrupts = <1>; 319 #clock-cells = <0>; 320 clocks = <&main>; 321 reg = <0>; 322 atmel,clk-input-range = <2000000 32000000>; 323 #atmel,pll-clk-output-range-cells = <4>; 324 atmel,pll-clk-output-ranges = <74500000 800000000 0 0 325 69500000 750000000 1 0 326 64500000 700000000 2 0 327 59500000 650000000 3 0 328 54500000 600000000 0 1 329 49500000 550000000 1 1 330 44500000 500000000 2 1 331 40000000 450000000 3 1>; 332 }; 333 334Required properties for plldiv clocks (plldiv = pll / 2): 335- #clock-cells : from common clock binding; shall be set to 0. 336- clocks : shall be the plla clock phandle. 337 338The pll divisor is equal to 2 and cannot be changed. 339 340For example: 341 plladiv: plladivck { 342 compatible = "atmel,at91sam9x5-clk-plldiv"; 343 #clock-cells = <0>; 344 clocks = <&plla>; 345 }; 346 347Required properties for programmable clocks: 348- #size-cells : shall be 0 (reg is used to encode clk id). 349- #address-cells : shall be 1 (reg is used to encode clk id). 350- clocks : shall be the programmable clock source phandles. 351 e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; 352- name: device tree node describing a specific prog clock. 353 * #clock-cells : from common clock binding; shall be set to 0. 354 * reg : programmable clock id (register offset from PCKx 355 register). 356 * interrupts : shall be set to "<(8 + id)>". 357 358For example: 359 prog: progck { 360 compatible = "atmel,at91sam9g45-clk-programmable"; 361 #size-cells = <0>; 362 #address-cells = <1>; 363 interrupt-parent = <&pmc>; 364 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; 365 366 prog0 { 367 #clock-cells = <0>; 368 reg = <0>; 369 interrupts = <8>; 370 }; 371 372 prog1 { 373 #clock-cells = <0>; 374 reg = <1>; 375 interrupts = <9>; 376 }; 377 }; 378 379 380Required properties for smd clock: 381- #clock-cells : from common clock binding; shall be set to 0. 382- clocks : shall be the smd clock source phandles. 383 e.g. clocks = <&plladiv>, <&utmi>; 384 385For example: 386 smd: smdck { 387 compatible = "atmel,at91sam9x5-clk-smd"; 388 #clock-cells = <0>; 389 clocks = <&plladiv>, <&utmi>; 390 }; 391 392Required properties for system clocks: 393- #size-cells : shall be 0 (reg is used to encode clk id). 394- #address-cells : shall be 1 (reg is used to encode clk id). 395- name: device tree node describing a specific system clock. 396 * #clock-cells : from common clock binding; shall be set to 0. 397 * reg: system clock id (bit position in SCER/SCDR/SCSR registers). 398 See Atmel's datasheet to get a full list of system clock ids. 399 400For example: 401 system: systemck { 402 compatible = "atmel,at91rm9200-clk-system"; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 406 ddrck { 407 #clock-cells = <0>; 408 reg = <2>; 409 clocks = <&mck>; 410 }; 411 412 uhpck { 413 #clock-cells = <0>; 414 reg = <6>; 415 clocks = <&usb>; 416 }; 417 418 udpck { 419 #clock-cells = <0>; 420 reg = <7>; 421 clocks = <&usb>; 422 }; 423 }; 424 425 426Required properties for usb clock: 427- #clock-cells : from common clock binding; shall be set to 0. 428- clocks : shall be the smd clock source phandles. 429 e.g. clocks = <&pllb>; 430- atmel,clk-divisors (only available for "atmel,at91rm9200-clk-usb"): 431 usb clock divisor table. 432 e.g. divisors = <1 2 4 0>; 433 434For example: 435 usb: usbck { 436 compatible = "atmel,at91sam9x5-clk-usb"; 437 #clock-cells = <0>; 438 clocks = <&plladiv>, <&utmi>; 439 }; 440 441 usb: usbck { 442 compatible = "atmel,at91rm9200-clk-usb"; 443 #clock-cells = <0>; 444 clocks = <&pllb>; 445 atmel,clk-divisors = <1 2 4 0>; 446 }; 447 448 449Required properties for utmi clock: 450- interrupts : shall be set to "<AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>". 451- #clock-cells : from common clock binding; shall be set to 0. 452- clocks : shall be the main clock source phandle. 453 454For example: 455 utmi: utmick { 456 compatible = "atmel,at91sam9x5-clk-utmi"; 457 interrupt-parent = <&pmc>; 458 interrupts = <AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>; 459 #clock-cells = <0>; 460 clocks = <&main>; 461 }; 462 463Required properties for 32 bits bus Matrix clock (h32mx clock): 464- #clock-cells : from common clock binding; shall be set to 0. 465- clocks : shall be the master clock source phandle. 466 467For example: 468 h32ck: h32mxck { 469 #clock-cells = <0>; 470 compatible = "atmel,sama5d4-clk-h32mx"; 471 clocks = <&mck>; 472 }; 473 474Required properties for generated clocks: 475- #size-cells : shall be 0 (reg is used to encode clk id). 476- #address-cells : shall be 1 (reg is used to encode clk id). 477- clocks : shall be the generated clock source phandles. 478 e.g. clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>; 479- name: device tree node describing a specific generated clock. 480 * #clock-cells : from common clock binding; shall be set to 0. 481 * reg: peripheral id. See Atmel's datasheets to get a full 482 list of peripheral ids. 483 * atmel,clk-output-range : minimum and maximum clock frequency 484 (two u32 fields). 485 486For example: 487 gck { 488 compatible = "atmel,sama5d2-clk-generated"; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>; 492 493 tcb0_gclk: tcb0_gclk { 494 #clock-cells = <0>; 495 reg = <35>; 496 atmel,clk-output-range = <0 83000000>; 497 }; 498 499 pwm_gclk: pwm_gclk { 500 #clock-cells = <0>; 501 reg = <38>; 502 atmel,clk-output-range = <0 83000000>; 503 }; 504 }; 505 506Required properties for I2S mux clocks: 507- #size-cells : shall be 0 (reg is used to encode I2S bus id). 508- #address-cells : shall be 1 (reg is used to encode I2S bus id). 509- name: device tree node describing a specific mux clock. 510 * #clock-cells : from common clock binding; shall be set to 0. 511 * clocks : shall be the mux clock parent phandles; shall be 2 phandles: 512 peripheral and generated clock; the first phandle shall belong to the 513 peripheral clock and the second one shall belong to the generated 514 clock; "clock-indices" property can be user to specify 515 the correct order. 516 * reg: I2S bus id of the corresponding mux clock. 517 e.g. reg = <0>; for i2s0, reg = <1>; for i2s1 518 519For example: 520 i2s_clkmux { 521 compatible = "atmel,sama5d2-clk-i2s-mux"; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 525 i2s0muxck: i2s0_muxclk { 526 clocks = <&i2s0_clk>, <&i2s0_gclk>; 527 #clock-cells = <0>; 528 reg = <0>; 529 }; 530 531 i2s1muxck: i2s1_muxclk { 532 clocks = <&i2s1_clk>, <&i2s1_gclk>; 533 #clock-cells = <0>; 534 reg = <1>; 535 }; 536 }; 537