| /kernel/linux/linux-4.19/drivers/gpu/drm/omapdrm/dss/ |
| D | dispc.c | 21 #define DSS_SUBSYS_NAME "DISPC"
48 #include "dispc.h"
52 /* DISPC */
61 #define REG_GET(dispc, idx, start, end) \ argument
62 FLD_GET(dispc_read_reg(dispc, idx), start, end)
64 #define REG_FLD_MOD(dispc, idx, val, start, end) \ argument
65 dispc_write_reg(dispc, idx, \
66 FLD_MOD(dispc_read_reg(dispc, idx), val, start, end))
68 /* DISPC has feature id */
111 int (*calc_scaling)(struct dispc_device *dispc,
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| D | omapdss.h | 507 /* DISPC channel for this output */
688 /* dispc ops */
691 u32 (*read_irqstatus)(struct dispc_device *dispc);
692 void (*clear_irqstatus)(struct dispc_device *dispc, u32 mask);
693 void (*write_irqenable)(struct dispc_device *dispc, u32 mask);
695 int (*request_irq)(struct dispc_device *dispc, irq_handler_t handler,
697 void (*free_irq)(struct dispc_device *dispc, void *dev_id);
699 int (*runtime_get)(struct dispc_device *dispc);
700 void (*runtime_put)(struct dispc_device *dispc);
702 int (*get_num_ovls)(struct dispc_device *dispc);
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| D | dss.h | 268 struct dispc_device *dispc; member
401 /* DISPC */
402 void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s);
404 int dispc_runtime_get(struct dispc_device *dispc);
405 void dispc_runtime_put(struct dispc_device *dispc);
407 void dispc_enable_sidle(struct dispc_device *dispc);
408 void dispc_disable_sidle(struct dispc_device *dispc);
410 void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable);
411 void dispc_pck_free_enable(struct dispc_device *dispc, bool enable);
412 void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable);
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| /kernel/linux/linux-5.10/drivers/gpu/drm/omapdrm/dss/ |
| D | dispc.c | 10 #define DSS_SUBSYS_NAME "DISPC"
37 #include "dispc.h"
41 /* DISPC */
50 #define REG_GET(dispc, idx, start, end) \ argument
51 FLD_GET(dispc_read_reg(dispc, idx), start, end)
53 #define REG_FLD_MOD(dispc, idx, val, start, end) \ argument
54 dispc_write_reg(dispc, idx, \
55 FLD_MOD(dispc_read_reg(dispc, idx), val, start, end))
57 /* DISPC has feature id */
100 int (*calc_scaling)(struct dispc_device *dispc,
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| D | omapdss.h | 404 /* DISPC channel for this output */
523 /* dispc ops */
526 u32 (*read_irqstatus)(struct dispc_device *dispc);
527 void (*clear_irqstatus)(struct dispc_device *dispc, u32 mask);
528 void (*write_irqenable)(struct dispc_device *dispc, u32 mask);
530 int (*request_irq)(struct dispc_device *dispc, irq_handler_t handler,
532 void (*free_irq)(struct dispc_device *dispc, void *dev_id);
534 int (*runtime_get)(struct dispc_device *dispc);
535 void (*runtime_put)(struct dispc_device *dispc);
537 int (*get_num_ovls)(struct dispc_device *dispc);
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| D | dss.h | 259 struct dispc_device *dispc; member
390 /* DISPC */
391 void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s);
393 int dispc_runtime_get(struct dispc_device *dispc);
394 void dispc_runtime_put(struct dispc_device *dispc);
396 void dispc_enable_sidle(struct dispc_device *dispc);
397 void dispc_disable_sidle(struct dispc_device *dispc);
399 void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable);
400 void dispc_pck_free_enable(struct dispc_device *dispc, bool enable);
401 void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable);
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| /kernel/linux/linux-5.10/drivers/gpu/drm/tidss/ |
| D | tidss_dispc.c | 310 static void dispc_write(struct dispc_device *dispc, u16 reg, u32 val) in dispc_write() argument
312 iowrite32(val, dispc->base_common + reg); in dispc_write()
315 static u32 dispc_read(struct dispc_device *dispc, u16 reg) in dispc_read() argument
317 return ioread32(dispc->base_common + reg); in dispc_read()
321 void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val) in dispc_vid_write() argument
323 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_write()
328 static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg) in dispc_vid_read() argument
330 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_read()
335 static void dispc_ovr_write(struct dispc_device *dispc, u32 hw_videoport, in dispc_ovr_write() argument
338 void __iomem *base = dispc->base_ovr[hw_videoport]; in dispc_ovr_write()
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| D | tidss_dispc.h | 92 void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask);
93 dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc);
95 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,
97 void dispc_ovr_enable_layer(struct dispc_device *dispc,
100 void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport,
102 void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,
104 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport);
105 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport);
106 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport);
107 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport);
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| D | tidss_crtc.c | 40 busy = dispc_vp_go_busy(tidss->dispc, tcrtc->hw_videoport); in tidss_crtc_finish_page_flip()
92 struct dispc_device *dispc = tidss->dispc; in tidss_crtc_atomic_check() local
105 ok = dispc_vp_mode_valid(dispc, hw_videoport, mode); in tidss_crtc_atomic_check()
112 return dispc_vp_bus_check(dispc, hw_videoport, state); in tidss_crtc_atomic_check()
153 dispc_ovr_set_plane(tidss->dispc, tplane->hw_plane_id, in tidss_crtc_position_planes()
158 dispc_ovr_enable_layer(tidss->dispc, tcrtc->hw_videoport, layer, in tidss_crtc_position_planes()
188 if (WARN_ON(dispc_vp_go_busy(tidss->dispc, tcrtc->hw_videoport))) in tidss_crtc_atomic_flush()
196 dispc_vp_setup(tidss->dispc, tcrtc->hw_videoport, crtc->state, false); in tidss_crtc_atomic_flush()
204 dispc_vp_go(tidss->dispc, tcrtc->hw_videoport); in tidss_crtc_atomic_flush()
228 r = dispc_vp_set_clk_rate(tidss->dispc, tcrtc->hw_videoport, in tidss_crtc_atomic_enable()
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| D | tidss_irq.c | 15 /* call with wait_lock and dispc runtime held */
20 dispc_set_irqenable(tidss->dispc, tidss->irq_mask); in tidss_irq_update()
63 irqstatus = dispc_read_and_clear_irqstatus(tidss->dispc); in tidss_irq_handler()
104 dispc_set_irqenable(tidss->dispc, 0); in tidss_irq_preinstall()
105 dispc_read_and_clear_irqstatus(tidss->dispc); in tidss_irq_preinstall()
144 dispc_set_irqenable(tidss->dispc, 0); in tidss_irq_uninstall()
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| D | tidss_drv.c | 57 return dispc_runtime_suspend(tidss->dispc); in tidss_pm_runtime_suspend()
67 r = dispc_runtime_resume(tidss->dispc); in tidss_pm_runtime_resume()
152 dev_err(dev, "failed to initialize dispc: %d\n", ret); in tidss_probe()
160 dispc_runtime_resume(tidss->dispc); in tidss_probe()
203 dispc_runtime_suspend(tidss->dispc); in tidss_probe()
226 dispc_runtime_suspend(tidss->dispc); in tidss_remove()
230 /* devm allocated dispc goes away with the dev so mark it NULL */ in tidss_remove()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/omapdrm/ |
| D | omap_irq.c | 18 /* call with wait_lock and dispc runtime held */
32 priv->dispc_ops->write_irqenable(priv->dispc, irqmask); in omap_irq_update()
86 priv->dispc_ops->mgr_get_framedone_irq(priv->dispc, channel); in omap_irq_enable_framedone()
124 priv->irq_mask |= priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, in omap_irq_enable_vblank()
151 priv->irq_mask &= ~priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, in omap_irq_disable_vblank()
216 irqstatus = priv->dispc_ops->read_irqstatus(priv->dispc); in omap_irq_handler()
217 priv->dispc_ops->clear_irqstatus(priv->dispc, irqstatus); in omap_irq_handler()
218 priv->dispc_ops->read_irqstatus(priv->dispc); /* flush posted write */ in omap_irq_handler()
226 if (irqstatus & priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel)) { in omap_irq_handler()
231 if (irqstatus & priv->dispc_ops->mgr_get_sync_lost_irq(priv->dispc, channel)) in omap_irq_handler()
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| D | omap_crtc.c | 106 priv->dispc_ops->mgr_enable(priv->dispc, channel, true); in omap_crtc_dss_start_update()
131 priv->dispc_ops->mgr_enable(priv->dispc, channel, enable); in omap_crtc_set_enabled()
144 framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(priv->dispc, in omap_crtc_set_enabled()
146 vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel); in omap_crtc_set_enabled()
153 * FRAMEDONE to know that DISPC has finished with the output. in omap_crtc_set_enabled()
166 priv->dispc_ops->mgr_enable(priv->dispc, channel, enable); in omap_crtc_set_enabled()
189 priv->dispc_ops->mgr_set_timings(priv->dispc, omap_crtc->channel, in omap_crtc_dss_enable()
224 priv->dispc_ops->mgr_set_lcd_config(priv->dispc, omap_crtc->channel, in omap_crtc_dss_set_lcd_config()
300 * If the dispc is busy we're racing the flush operation. Try again on in omap_crtc_vblank_irq()
303 if (priv->dispc_ops->mgr_go_busy(priv->dispc, omap_crtc->channel)) { in omap_crtc_vblank_irq()
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| /kernel/linux/linux-4.19/drivers/gpu/drm/omapdrm/ |
| D | omap_irq.c | 27 /* call with wait_lock and dispc runtime held */
41 priv->dispc_ops->write_irqenable(priv->dispc, irqmask); in omap_irq_update()
111 priv->irq_mask |= priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, in omap_irq_enable_vblank()
138 priv->irq_mask &= ~priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, in omap_irq_disable_vblank()
203 irqstatus = priv->dispc_ops->read_irqstatus(priv->dispc); in omap_irq_handler()
204 priv->dispc_ops->clear_irqstatus(priv->dispc, irqstatus); in omap_irq_handler()
205 priv->dispc_ops->read_irqstatus(priv->dispc); /* flush posted write */ in omap_irq_handler()
213 if (irqstatus & priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel)) { in omap_irq_handler()
218 if (irqstatus & priv->dispc_ops->mgr_get_sync_lost_irq(priv->dispc, channel)) in omap_irq_handler()
245 * omapdrm are merged together we can assign the dispc hwmod data to
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| D | omap_crtc.c | 121 struct dispc_device *dispc = priv->dispc; in omap_crtc_dss_connect() local
126 if (!(dispc_ops->mgr_get_supported_outputs(dispc, channel) & dst->id)) in omap_crtc_dss_connect()
163 priv->dispc_ops->mgr_enable(priv->dispc, channel, enable); in omap_crtc_set_enabled()
176 framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(priv->dispc, in omap_crtc_set_enabled()
178 vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel); in omap_crtc_set_enabled()
185 * FRAMEDONE to know that DISPC has finished with the output. in omap_crtc_set_enabled()
198 priv->dispc_ops->mgr_enable(priv->dispc, channel, enable); in omap_crtc_set_enabled()
220 priv->dispc_ops->mgr_set_timings(priv->dispc, omap_crtc->channel, in omap_crtc_dss_enable()
251 priv->dispc_ops->mgr_set_lcd_config(priv->dispc, omap_crtc->channel, in omap_crtc_dss_set_lcd_config()
306 * If the dispc is busy we're racing the flush operation. Try again on in omap_crtc_vblank_irq()
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| /kernel/linux/linux-4.19/drivers/video/fbdev/omap2/omapfb/dss/ |
| D | dispc.c | 2 * linux/drivers/video/omap2/dss/dispc.c
23 #define DSS_SUBSYS_NAME "DISPC"
48 #include "dispc.h"
50 /* DISPC */
95 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
138 } dispc; variable
264 __raw_writel(val, dispc.base + idx); in dispc_write_reg()
269 return __raw_readl(dispc.base + idx); in dispc_read_reg()
285 spin_lock_irqsave(&dispc.control_lock, flags); in mgr_fld_write()
290 spin_unlock_irqrestore(&dispc.control_lock, flags); in mgr_fld_write()
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| /kernel/linux/linux-5.10/drivers/video/fbdev/omap2/omapfb/dss/ |
| D | dispc.c | 3 * linux/drivers/video/omap2/dss/dispc.c
12 #define DSS_SUBSYS_NAME "DISPC"
37 #include "dispc.h"
39 /* DISPC */
84 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
127 } dispc; variable
253 __raw_writel(val, dispc.base + idx); in dispc_write_reg()
258 return __raw_readl(dispc.base + idx); in dispc_read_reg()
274 spin_lock_irqsave(&dispc.control_lock, flags); in mgr_fld_write()
279 spin_unlock_irqrestore(&dispc.control_lock, flags); in mgr_fld_write()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/ti/ |
| D | ti,dra7-dss.txt | 29 - DISPC
39 DISPC
43 - compatible: "ti,dra7-dispc"
46 - interrupts: the DISPC interrupt
51 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
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| D | ti,omap5-dss.txt | 18 - DISPC
28 DISPC
32 - compatible: "ti,omap5-dispc"
35 - interrupts: the DISPC interrupt
40 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
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| D | ti,omap2-dss.txt | 22 DISPC
26 - compatible: "ti,omap2-dispc"
29 - interrupts: the DISPC interrupt
32 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
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| D | ti,omap4-dss.txt | 18 - DISPC
28 DISPC
32 - compatible: "ti,omap4-dispc"
35 - interrupts: the DISPC interrupt
40 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/ti/ |
| D | ti,dra7-dss.txt | 29 - DISPC
39 DISPC
43 - compatible: "ti,dra7-dispc"
46 - interrupts: the DISPC interrupt
51 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
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| D | ti,omap5-dss.txt | 18 - DISPC
28 DISPC
32 - compatible: "ti,omap5-dispc"
35 - interrupts: the DISPC interrupt
40 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
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| D | ti,omap2-dss.txt | 22 DISPC
26 - compatible: "ti,omap2-dispc"
29 - interrupts: the DISPC interrupt
32 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
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| D | ti,omap4-dss.txt | 18 - DISPC
28 DISPC
32 - compatible: "ti,omap4-dispc"
35 - interrupts: the DISPC interrupt
40 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
|