| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/dma/ |
| D | brcm,bcm2835-dma.txt | 1 * BCM2835 DMA controller
3 The BCM2835 DMA controller has 16 channels in total.
4 Only the lower 13 channels have an associated IRQ.
5 Some arbitrary channels are used by the firmware
7 The channels 0,2 and 3 have special functionality
11 - compatible: Should be "brcm,bcm2835-dma".
12 - reg: Should contain DMA registers location and length.
13 - interrupts: Should contain the DMA interrupts associated
14 to the DMA channels in ascending order.
15 - interrupt-names: Should contain the names of the interrupt
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| D | jz4780-dma.txt | 1 * Ingenic JZ4780 DMA Controller
5 - compatible: Should be "ingenic,jz4780-dma"
6 - reg: Should contain the DMA controller registers location and length.
7 - interrupts: Should contain the interrupt specifier of the DMA controller.
8 - clocks: Should contain a clock specifier for the JZ4780 PDMA clock.
9 - #dma-cells: Must be <2>. Number of integer cells in the dmas property of
10 DMA clients (see below).
14 - ingenic,reserved-channels: Bitmask of channels to reserve for devices that
15 need a specific channel. These channels will only be assigned when explicitly
16 requested by a client. The primary use for this is channels 0 and 1, which
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| D | ste-dma40.txt | 1 * DMA40 DMA Controller
4 - compatible: "stericsson,dma40"
5 - reg: Address range of the DMAC registers
6 - reg-names: Names of the above areas to use during resource look-up
7 - interrupt: Should contain the DMAC interrupt number
8 - #dma-cells: must be <3>
9 - memcpy-channels: Channels to be used for memcpy
12 - dma-channels: Number of channels supported by hardware - if not present
14 - disabled-channels: Channels which can not be used
18 dma: dma-controller@801c0000 {
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| D | renesas,rcar-dmac.txt | 1 * Renesas R-Car (RZ/G) DMA Controller Device Tree bindings
3 Renesas R-Car Generation 2 SoCs have multiple multi-channel DMA
4 controller instances named DMAC capable of serving multiple clients. Channels
8 Each DMA client is connected to one dedicated port of the DMAC, identified by
9 an 8-bit port number called the MID/RID. A DMA controller can thus serve up to
10 256 clients in total. When the number of hardware channels is lower than the
11 number of clients to be served, channels must be shared between multiple DMA
12 clients. The association of DMA clients to DMAC channels is fully dynamic and
17 - compatible: "renesas,dmac-<soctype>", "renesas,rcar-dmac" as fallback.
19 - "renesas,dmac-r8a7743" (RZ/G1M)
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| D | mmp-dma.txt | 1 * MARVELL MMP DMA controller
3 Marvell Peripheral DMA Controller
7 - compatible: Should be "marvell,pdma-1.0"
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Either contain all of the per-channel DMA interrupts
13 - #dma-channels: Number of DMA channels supported by the controller (defaults
15 - #dma-requests: Number of DMA requestor lines supported by the controller
18 "marvell,pdma-1.0"
26 * while DMA controller may not able to distinguish the irq channel
27 * Using this method, interrupt-parent is required as demuxer
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| D | snps,dw-axi-dmac.txt | 1 Synopsys DesignWare AXI DMA Controller
4 - compatible: "snps,axi-dma-1.01a"
5 - reg: Address range of the DMAC registers. This should include
6 all of the per-channel registers.
7 - interrupt: Should contain the DMAC interrupt number.
8 - dma-channels: Number of channels supported by hardware.
9 - snps,dma-masters: Number of AXI masters supported by the hardware.
10 - snps,data-width: Maximum AXI data width supported by hardware.
11 (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
12 - snps,priority: Priority of channel. Array size is equal to the number of
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| D | fsl-mxs-dma.txt | 1 * Freescale MXS DMA
4 - compatible : Should be "fsl,<chip>-dma-apbh" or "fsl,<chip>-dma-apbx"
5 - reg : Should contain registers location and length
6 - interrupts : Should contain the interrupt numbers of DMA channels.
8 - #dma-cells : Must be <1>. The number cell specifies the channel ID.
9 - dma-channels : Number of channels supported by the DMA controller
12 - interrupt-names : Name of DMA channel interrupts
19 dma_apbh: dma-apbh@80004000 {
20 compatible = "fsl,imx28-dma-apbh";
26 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
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| D | snps-dma.txt | 1 * Synopsys Designware DMA Controller
4 - compatible: "snps,dma-spear1340"
5 - reg: Address range of the DMAC registers
6 - interrupt: Should contain the DMAC interrupt number
7 - dma-channels: Number of channels supported by hardware
8 - dma-requests: Number of DMA request lines supported, up to 16
9 - dma-masters: Number of AHB masters supported by the controller
10 - #dma-cells: must be <3>
11 - chan_allocation_order: order of allocation of channel, 0 (default): ascending,
13 - chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/ |
| D | brcm,bcm2835-dma.txt | 1 * BCM2835 DMA controller
3 The BCM2835 DMA controller has 16 channels in total.
4 Only the lower 13 channels have an associated IRQ.
5 Some arbitrary channels are used by the firmware
7 The channels 0,2 and 3 have special functionality
11 - compatible: Should be "brcm,bcm2835-dma".
12 - reg: Should contain DMA registers location and length.
13 - interrupts: Should contain the DMA interrupts associated
14 to the DMA channels in ascending order.
15 - interrupt-names: Should contain the names of the interrupt
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| D | ste-dma40.txt | 1 * DMA40 DMA Controller
4 - compatible: "stericsson,dma40"
5 - reg: Address range of the DMAC registers
6 - reg-names: Names of the above areas to use during resource look-up
7 - interrupt: Should contain the DMAC interrupt number
8 - #dma-cells: must be <3>
9 - memcpy-channels: Channels to be used for memcpy
12 - dma-channels: Number of channels supported by hardware - if not present
14 - disabled-channels: Channels which can not be used
18 dma: dma-controller@801c0000 {
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| D | ingenic,dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/ingenic,dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs DMA Controller DT bindings
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: "dma-controller.yaml#"
18 - ingenic,jz4740-dma
19 - ingenic,jz4725b-dma
20 - ingenic,jz4770-dma
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| D | mmp-dma.txt | 1 * MARVELL MMP DMA controller
3 Marvell Peripheral DMA Controller
7 - compatible: Should be "marvell,pdma-1.0"
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Either contain all of the per-channel DMA interrupts
13 - #dma-channels: Number of DMA channels supported by the controller (defaults
15 - #dma-requests: Number of DMA requestor lines supported by the controller
18 "marvell,pdma-1.0"
26 * while DMA controller may not able to distinguish the irq channel
27 * Using this method, interrupt-parent is required as demuxer
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| D | owl-dma.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/owl-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Actions Semi Owl SoCs DMA controller
10 The OWL DMA is a general-purpose direct memory access controller capable of
11 supporting 10 and 12 independent DMA channels for S700 and S900 SoCs
15 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 - $ref: "dma-controller.yaml#"
23 - actions,s900-dma
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| D | dma-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/dma-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DMA Engine Generic Binding
10 - Vinod Koul <vkoul@kernel.org>
13 Generic binding to provide a way for a driver using DMA Engine to
14 retrieve the DMA request or channel information that goes from a
15 hardware device to a DMA controller.
20 "#dma-cells":
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| D | snps,dw-axi-dmac.txt | 1 Synopsys DesignWare AXI DMA Controller
4 - compatible: "snps,axi-dma-1.01a"
5 - reg: Address range of the DMAC registers. This should include
6 all of the per-channel registers.
7 - interrupt: Should contain the DMAC interrupt number.
8 - dma-channels: Number of channels supported by hardware.
9 - snps,dma-masters: Number of AXI masters supported by the hardware.
10 - snps,data-width: Maximum AXI data width supported by hardware.
11 (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
12 - snps,priority: Priority of channel. Array size is equal to the number of
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| D | fsl-mxs-dma.txt | 1 * Freescale MXS DMA
4 - compatible : Should be "fsl,<chip>-dma-apbh" or "fsl,<chip>-dma-apbx"
5 - reg : Should contain registers location and length
6 - interrupts : Should contain the interrupt numbers of DMA channels.
8 - #dma-cells : Must be <1>. The number cell specifies the channel ID.
9 - dma-channels : Number of channels supported by the DMA controller
12 - interrupt-names : Name of DMA channel interrupts
19 dma_apbh: dma-apbh@80004000 {
20 compatible = "fsl,imx28-dma-apbh";
26 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
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| /kernel/linux/linux-5.10/arch/arm/mach-ep93xx/ |
| D | dma.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/mach-ep93xx/dma.c
9 * This work is based on the original dma-m2p implementation with
18 #include <linux/dma-mapping.h>
24 #include <linux/platform_data/dma-ep93xx.h>
33 * DMA M2P channels.
36 * Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive).
38 * I2S contains 3 Tx and 3 Rx DMA Channels
39 * AAC contains 3 Tx and 3 Rx DMA Channels
40 * UART1 contains 1 Tx and 1 Rx DMA Channels
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| /kernel/linux/linux-4.19/arch/arm/mach-ep93xx/ |
| D | dma.c | 2 * arch/arm/mach-ep93xx/dma.c
8 * This work is based on the original dma-m2p implementation with
22 #include <linux/dma-mapping.h>
28 #include <linux/platform_data/dma-ep93xx.h>
37 * DMA M2P channels.
40 * Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive).
42 * I2S contains 3 Tx and 3 Rx DMA Channels
43 * AAC contains 3 Tx and 3 Rx DMA Channels
44 * UART1 contains 1 Tx and 1 Rx DMA Channels
45 * UART2 contains 1 Tx and 1 Rx DMA Channels
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| /kernel/linux/linux-4.19/drivers/iio/adc/ |
| D | ti_am335x_adc.c | 4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
34 #include <linux/dma-mapping.h>
51 struct tiadc_dma dma; member
53 int channels; member
64 return readl(adc->mfd_tscadc->tscadc_base + reg); in tiadc_readl()
70 writel(val, adc->mfd_tscadc->tscadc_base + reg); in tiadc_writel()
77 step_en = ((1 << adc_dev->channels) - 1); in get_adc_step_mask()
78 step_en <<= TOTAL_STEPS - adc_dev->channels + 1; in get_adc_step_mask()
87 for (i = 0; i < ARRAY_SIZE(adc_dev->channel_step); i++) { in get_adc_chan_step_mask()
88 if (chan->channel == adc_dev->channel_line[i]) { in get_adc_chan_step_mask()
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| /kernel/linux/linux-5.10/drivers/iio/adc/ |
| D | ti_am335x_adc.c | 4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
34 #include <linux/dma-mapping.h>
51 struct tiadc_dma dma; member
53 int channels; member
64 return readl(adc->mfd_tscadc->tscadc_base + reg); in tiadc_readl()
70 writel(val, adc->mfd_tscadc->tscadc_base + reg); in tiadc_writel()
77 step_en = ((1 << adc_dev->channels) - 1); in get_adc_step_mask()
78 step_en <<= TOTAL_STEPS - adc_dev->channels + 1; in get_adc_step_mask()
87 for (i = 0; i < ARRAY_SIZE(adc_dev->channel_step); i++) { in get_adc_chan_step_mask()
88 if (chan->channel == adc_dev->channel_line[i]) { in get_adc_chan_step_mask()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/xilinx/ |
| D | xilinx_dma.txt | 2 It can be configured to have one channel or two channels. If configured
3 as two channels, one is to transmit to the video device and another is
6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
7 target devices. It can be configured to have one channel or two channels.
8 If configured as two channels, one is to transmit to the device and another
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
16 and receive channels.
19 - compatible: Should be one of-
20 "xlnx,axi-vdma-1.00.a"
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/sound/ |
| D | rockchip-i2s.txt | 3 The I2S bus (Inter-IC sound bus) is a serial link for digital
8 - compatible: should be one of the following:
9 - "rockchip,rk3066-i2s": for rk3066
10 - "rockchip,px30-i2s", "rockchip,rk3066-i2s": for px30
11 - "rockchip,rk3036-i2s", "rockchip,rk3066-i2s": for rk3036
12 - "rockchip,rk3188-i2s", "rockchip,rk3066-i2s": for rk3188
13 - "rockchip,rk3228-i2s", "rockchip,rk3066-i2s": for rk3228
14 - "rockchip,rk3288-i2s", "rockchip,rk3066-i2s": for rk3288
15 - "rockchip,rk3328-i2s", "rockchip,rk3066-i2s": for rk3328
16 - "rockchip,rk3366-i2s", "rockchip,rk3066-i2s": for rk3366
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/dma/xilinx/ |
| D | xilinx_dma.txt | 2 It can be configured to have one channel or two channels. If configured
3 as two channels, one is to transmit to the video device and another is
6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
7 target devices. It can be configured to have one channel or two channels.
8 If configured as two channels, one is to transmit to the device and another
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
15 - compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or
16 "xlnx,axi-cdma-1.00.a""
17 - #dma-cells: Should be <1>, see "dmas" property below
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| /kernel/linux/linux-5.10/include/linux/platform_data/ |
| D | dma-ep93xx.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/dma-mapping.h>
10 * M2P channels.
25 /* M2M channels */
30 * struct ep93xx_dma_data - configuration data for the EP93xx dmaengine
36 * function. Note that this is only needed for slave/cyclic channels. For
37 * memcpy channels %NULL data should be passed.
46 * struct ep93xx_dma_chan_data - platform specific data for a DMA channel
58 * struct ep93xx_dma_platform_data - platform data for the dmaengine driver
59 * @channels: array of channels which are passed to the driver
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| /kernel/linux/linux-4.19/include/linux/platform_data/ |
| D | dma-ep93xx.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/dma-mapping.h>
10 * M2P channels.
25 /* M2M channels */
30 * struct ep93xx_dma_data - configuration data for the EP93xx dmaengine
36 * function. Note that this is only needed for slave/cyclic channels. For
37 * memcpy channels %NULL data should be passed.
46 * struct ep93xx_dma_chan_data - platform specific data for a DMA channel
58 * struct ep93xx_dma_platform_data - platform data for the dmaengine driver
59 * @channels: array of channels which are passed to the driver
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