1* Ingenic JZ4780 DMA Controller 2 3Required properties: 4 5- compatible: Should be "ingenic,jz4780-dma" 6- reg: Should contain the DMA controller registers location and length. 7- interrupts: Should contain the interrupt specifier of the DMA controller. 8- clocks: Should contain a clock specifier for the JZ4780 PDMA clock. 9- #dma-cells: Must be <2>. Number of integer cells in the dmas property of 10 DMA clients (see below). 11 12Optional properties: 13 14- ingenic,reserved-channels: Bitmask of channels to reserve for devices that 15 need a specific channel. These channels will only be assigned when explicitly 16 requested by a client. The primary use for this is channels 0 and 1, which 17 can be configured to have special behaviour for NAND/BCH when using 18 programmable firmware. 19 20Example: 21 22dma: dma@13420000 { 23 compatible = "ingenic,jz4780-dma"; 24 reg = <0x13420000 0x10000>; 25 26 interrupt-parent = <&intc>; 27 interrupts = <10>; 28 29 clocks = <&cgu JZ4780_CLK_PDMA>; 30 31 #dma-cells = <2>; 32 33 ingenic,reserved-channels = <0x3>; 34}; 35 36DMA clients must use the format described in dma.txt, giving a phandle to the 37DMA controller plus the following 2 integer cells: 38 391. Request type: The DMA request type for transfers to/from the device on 40 the allocated channel, as defined in the SoC documentation. 41 422. Channel: If set to 0xffffffff, any available channel will be allocated for 43 the client. Otherwise, the exact channel specified will be used. The channel 44 should be reserved on the DMA controller using the ingenic,reserved-channels 45 property. 46 47Example: 48 49uart0: serial@10030000 { 50 ... 51 dmas = <&dma 0x14 0xffffffff 52 &dma 0x15 0xffffffff>; 53 dma-names = "tx", "rx"; 54 ... 55}; 56