| /kernel/linux/linux-5.10/drivers/phy/cadence/ |
| D | cdns-dphy.c | 16 #include <linux/phy/phy-mipi-dphy.h>
21 /* DPHY registers */
76 int (*probe)(struct cdns_dphy *dphy);
77 void (*remove)(struct cdns_dphy *dphy);
78 void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
79 void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
81 void (*set_pll_cfg)(struct cdns_dphy *dphy,
83 unsigned long (*get_wakeup_time_ns)(struct cdns_dphy *dphy);
95 static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy, in cdns_dsi_get_dphy_pll_cfg() argument
100 unsigned long pll_ref_hz = clk_get_rate(dphy->pll_ref_clk); in cdns_dsi_get_dphy_pll_cfg()
[all …]
|
| /kernel/linux/linux-4.19/drivers/gpu/drm/sun4i/ |
| D | sun6i_mipi_dphy.c | 84 int sun6i_dphy_init(struct sun6i_dphy *dphy, unsigned int lanes) in sun6i_dphy_init() argument
86 reset_control_deassert(dphy->reset); in sun6i_dphy_init()
87 clk_prepare_enable(dphy->mod_clk); in sun6i_dphy_init()
88 clk_set_rate_exclusive(dphy->mod_clk, 150000000); in sun6i_dphy_init()
90 regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG, in sun6i_dphy_init()
93 regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG, in sun6i_dphy_init()
98 regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG, in sun6i_dphy_init()
104 regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG, in sun6i_dphy_init()
107 regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0); in sun6i_dphy_init()
109 regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG, in sun6i_dphy_init()
[all …]
|
| D | sun6i_mipi_dsi.h | 32 struct sun6i_dphy *dphy; member
58 int sun6i_dphy_init(struct sun6i_dphy *dphy, unsigned int lanes);
59 int sun6i_dphy_power_on(struct sun6i_dphy *dphy, unsigned int lanes);
60 int sun6i_dphy_power_off(struct sun6i_dphy *dphy);
61 int sun6i_dphy_exit(struct sun6i_dphy *dphy);
|
| /kernel/linux/linux-5.10/drivers/phy/allwinner/ |
| D | phy-sun6i-mipi-dphy.c | 18 #include <linux/phy/phy-mipi-dphy.h>
99 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_init() local
101 reset_control_deassert(dphy->reset); in sun6i_dphy_init()
102 clk_prepare_enable(dphy->mod_clk); in sun6i_dphy_init()
103 clk_set_rate_exclusive(dphy->mod_clk, 150000000); in sun6i_dphy_init()
110 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_configure() local
117 memcpy(&dphy->config, opts, sizeof(dphy->config)); in sun6i_dphy_configure()
124 struct sun6i_dphy *dphy = phy_get_drvdata(phy); in sun6i_dphy_power_on() local
125 u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0); in sun6i_dphy_power_on()
127 regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG, in sun6i_dphy_power_on()
[all …]
|
| /kernel/linux/linux-4.19/drivers/gpu/drm/bridge/ |
| D | cdns-dsi.c | 425 /* DPHY registers */
494 int (*probe)(struct cdns_dphy *dphy);
495 void (*remove)(struct cdns_dphy *dphy);
496 void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
497 void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
499 void (*set_pll_cfg)(struct cdns_dphy *dphy,
501 unsigned long (*get_wakeup_time_ns)(struct cdns_dphy *dphy);
529 struct cdns_dphy *dphy; member
548 static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy, in cdns_dsi_get_dphy_pll_cfg() argument
558 unsigned long pll_ref_hz = clk_get_rate(dphy->pll_ref_clk); in cdns_dsi_get_dphy_pll_cfg()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | cdns,dphy.txt | 1 Cadence DPHY
4 Cadence DPHY block.
7 - compatible: should be set to "cdns,dphy".
8 - reg: physical base address and length of the DPHY registers.
9 - clocks: DPHY reference clocks.
14 dphy0: dphy@fd0e0000{
15 compatible = "cdns,dphy";
|
| D | rockchip-mipi-dphy-rx0.yaml | 4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
19 const: rockchip,rk3399-mipi-dphy-rx0
29 - const: dphy-ref
30 - const: dphy-cfg
65 mipi_dphy_rx0: mipi-dphy-rx0 {
66 compatible = "rockchip,rk3399-mipi-dphy-rx0";
70 clock-names = "dphy-ref", "dphy-cfg", "grf";
|
| D | rockchip,px30-dsi-dphy.yaml | 4 $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
7 title: Rockchip MIPI DPHY with additional LVDS/TTL modes
18 - rockchip,px30-dsi-dphy
19 - rockchip,rk3128-dsi-dphy
20 - rockchip,rk3368-dsi-dphy
61 compatible = "rockchip,px30-dsi-dphy";
|
| D | mixel,mipi-dsi-phy.txt | 9 - "fsl,imx8mq-mipi-dphy"
12 - "phy_ref": phandle and specifier referring to the DPHY ref clock
22 dphy: dphy@30a0030 {
23 compatible = "fsl,imx8mq-mipi-dphy";
|
| D | allwinner,sun6i-a31-mipi-dphy.yaml | 4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
19 - const: allwinner,sun6i-a31-mipi-dphy
21 - const: allwinner,sun50i-a64-mipi-dphy
22 - const: allwinner,sun6i-a31-mipi-dphy
53 compatible = "allwinner,sun6i-a31-mipi-dphy";
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/bridge/ |
| D | cdns,dsi.txt | 13 - phy-names: must contain "dphy".
34 Cadence DPHY
37 Cadence DPHY block.
40 - compatible: should be set to "cdns,dphy".
41 - reg: physical base address and length of the DPHY registers.
42 - clocks: DPHY reference clocks.
48 dphy0: dphy@fd0e0000{
49 compatible = "cdns,dphy";
63 phy-names = "dphy";
94 phy-names = "dphy";
|
| /kernel/linux/linux-5.10/drivers/media/platform/marvell-ccic/ |
| D | mmp-driver.c | 51 * calc the dphy register values
52 * There are three dphy registers being used.
53 * dphy[0] - CSI2_DPHY3
54 * dphy[1] - CSI2_DPHY5
55 * dphy[2] - CSI2_DPHY6
73 * dphy[0] - CSI2_DPHY3: in mmpcam_calc_dphy()
75 * defines the time that the DPHY in mmpcam_calc_dphy()
99 pdata->dphy[0] = in mmpcam_calc_dphy()
107 pdata->dphy[0] = in mmpcam_calc_dphy()
129 * dphy[2] - CSI2_DPHY6: in mmpcam_calc_dphy()
[all …]
|
| /kernel/linux/linux-4.19/drivers/media/platform/marvell-ccic/ |
| D | mmp-driver.c | 209 * calc the dphy register values
210 * There are three dphy registers being used.
211 * dphy[0] - CSI2_DPHY3
212 * dphy[1] - CSI2_DPHY5
213 * dphy[2] - CSI2_DPHY6
231 * dphy[0] - CSI2_DPHY3: in mmpcam_calc_dphy()
233 * defines the time that the DPHY in mmpcam_calc_dphy()
257 pdata->dphy[0] = in mmpcam_calc_dphy()
265 pdata->dphy[0] = in mmpcam_calc_dphy()
287 * dphy[2] - CSI2_DPHY6: in mmpcam_calc_dphy()
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/sunxi/ |
| D | sun6i-dsi.txt | 22 - phy-names: must be "dphy"
38 * allwinner,sun6i-a31-mipi-dphy
57 phy-names = "dphy";
86 compatible = "allwinner,sun6i-a31-mipi-dphy";
|
| /kernel/linux/linux-5.10/drivers/phy/rockchip/ |
| D | Kconfig | 13 tristate "Rockchip MIPI Synopsys DPHY RX0 driver"
18 Enable this to support the Rockchip MIPI Synopsys DPHY RX0
22 will be called phy-rockchip-dphy-rx0.
|
| D | phy-rockchip-dphy-rx0.c | 3 * Rockchip MIPI Synopsys DPHY RX0 driver
26 #include <linux/phy/phy-mipi-dphy.h>
65 "dphy-ref",
66 "dphy-cfg",
201 /* dphy start */ in rk_dphy_enable()
317 .compatible = "rockchip,rk3399-mipi-dphy-rx0",
381 .name = "rockchip-mipi-dphy-rx0",
388 MODULE_DESCRIPTION("Rockchip MIPI Synopsys DPHY RX0 driver");
|
| /kernel/linux/linux-5.10/drivers/staging/media/rkisp1/Documentation/devicetree/bindings/media/ |
| D | rockchip-isp1.yaml | 37 const: dphy
69 description: connection point for sensors at MIPI-DPHY RX0
136 phys = <&dphy>;
137 phy-names = "dphy";
|
| /kernel/linux/linux-4.19/drivers/staging/media/omap4iss/ |
| D | iss_csiphy.c | 98 reg = phy->dphy.ths_term << REGISTER0_THS_TERM_SHIFT; in csiphy_dphy_config()
99 reg |= phy->dphy.ths_settle << REGISTER0_THS_SETTLE_SHIFT; in csiphy_dphy_config()
104 reg = phy->dphy.tclk_term << REGISTER1_TCLK_TERM_SHIFT; in csiphy_dphy_config()
105 reg |= phy->dphy.tclk_miss << REGISTER1_CTRLCLK_DIV_FACTOR_SHIFT; in csiphy_dphy_config()
106 reg |= phy->dphy.tclk_settle << REGISTER1_TCLK_SETTLE_SHIFT; in csiphy_dphy_config()
215 csi2->phy->dphy = csi2phy; in omap4iss_csiphy_config()
|
| /kernel/linux/linux-5.10/drivers/staging/media/omap4iss/ |
| D | iss_csiphy.c | 94 reg = phy->dphy.ths_term << REGISTER0_THS_TERM_SHIFT; in csiphy_dphy_config()
95 reg |= phy->dphy.ths_settle << REGISTER0_THS_SETTLE_SHIFT; in csiphy_dphy_config()
100 reg = phy->dphy.tclk_term << REGISTER1_TCLK_TERM_SHIFT; in csiphy_dphy_config()
101 reg |= phy->dphy.tclk_miss << REGISTER1_CTRLCLK_DIV_FACTOR_SHIFT; in csiphy_dphy_config()
102 reg |= phy->dphy.tclk_settle << REGISTER1_TCLK_SETTLE_SHIFT; in csiphy_dphy_config()
211 csi2->phy->dphy = csi2phy; in omap4iss_csiphy_config()
|
| /kernel/linux/linux-5.10/drivers/video/fbdev/mmp/hw/ |
| D | mmp_ctrl.h | 1100 #define DSI_PHY_CTRL_3 0x08C /* DPHY Control Register 3 */
1108 #define DSI_PHY_RCOMP_0 0x0B0 /* DPHY Rcomp Control Register */
1111 #define DSI_PHY_TIME_0 0x0C0 /* DPHY Timing Control Register 0 */
1112 #define DSI_PHY_TIME_1 0x0C4 /* DPHY Timing Control Register 1 */
1113 #define DSI_PHY_TIME_2 0x0C8 /* DPHY Timing Control Register 2 */
1114 #define DSI_PHY_TIME_3 0x0CC /* DPHY Timing Control Register 3 */
1115 #define DSI_PHY_TIME_4 0x0D0 /* DPHY Timing Control Register 4 */
1116 #define DSI_PHY_TIME_5 0x0D4 /* DPHY Timing Control Register 5 */
1208 /* DSI_PHY_CTRL_2 0x0088 DPHY Control Register 2 */
1210 /* DPHY LP Receiver Enable */
[all …]
|
| /kernel/linux/linux-5.10/drivers/phy/freescale/ |
| D | phy-fsl-imx8-mipi-dphy.c | 19 /* DPHY registers */
81 /* DPHY PLL parameters */
85 /* DPHY register values */
107 .name = "mipi-dphy",
117 dev_err(&phy->dev, "Failed to write DPHY reg %d: %d\n", reg, in phy_write()
391 dev_err(&phy->dev, "Could not get DPHY lock (%d)!\n", ret); in mixel_dphy_power_on()
425 { .compatible = "fsl,imx8mq-mipi-dphy",
460 dev_err(dev, "Couldn't create the DPHY regmap\n"); in mixel_dphy_probe()
489 .name = "mixel-mipi-dphy",
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,dsi.txt | 17 - phy-names: must contain "dphy"
38 mipi_tx0: mipi-dphy@10215000 {
55 phy-names = "dphy";
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/ |
| D | nwl-dsi.yaml | 63 A phandle to the phy module representing the DPHY
67 - const: dphy
193 phys = <&dphy>;
194 phy-names = "dphy";
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,dsi.txt | 17 - phy-names: must contain "dphy"
45 mipi_tx0: mipi-dphy@10215000 {
65 phy-names = "dphy";
|
| /kernel/linux/linux-4.19/drivers/video/fbdev/mmp/hw/ |
| D | mmp_ctrl.h | 1114 #define DSI_PHY_CTRL_3 0x08C /* DPHY Control Register 3 */
1122 #define DSI_PHY_RCOMP_0 0x0B0 /* DPHY Rcomp Control Register */
1125 #define DSI_PHY_TIME_0 0x0C0 /* DPHY Timing Control Register 0 */
1126 #define DSI_PHY_TIME_1 0x0C4 /* DPHY Timing Control Register 1 */
1127 #define DSI_PHY_TIME_2 0x0C8 /* DPHY Timing Control Register 2 */
1128 #define DSI_PHY_TIME_3 0x0CC /* DPHY Timing Control Register 3 */
1129 #define DSI_PHY_TIME_4 0x0D0 /* DPHY Timing Control Register 4 */
1130 #define DSI_PHY_TIME_5 0x0D4 /* DPHY Timing Control Register 5 */
1222 /* DSI_PHY_CTRL_2 0x0088 DPHY Control Register 2 */
1224 /* DPHY LP Receiver Enable */
[all …]
|