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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dstm32mp15-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
9 adc1_in6_pins_a: adc1-in6-0 {
15 adc12_ain_pins_a: adc12-ain-0 {
24 adc12_ain_pins_b: adc12-ain-1 {
31 adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
38 cec_pins_a: cec-0 {
41 bias-disable;
42 drive-open-drain;
[all …]
Dstm32f7-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
7 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
8 #include <dt-bindings/mfd/stm32f7-rcc.h>
12 pinctrl: pin-controller {
13 #address-cells = <1>;
14 #size-cells = <1>;
16 interrupt-parent = <&exti>;
18 pins-are-numbered;
21 gpio-controller;
[all …]
Dstm32h743-pinctrl.dtsi2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
47 pin-controller {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "st,stm32h743-pinctrl";
52 interrupt-parent = <&exti>;
54 pins-are-numbered;
57 gpio-controller;
[all …]
Dstm32f4-pinctrl.dtsi2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
44 #include <dt-bindings/mfd/stm32f4-rcc.h>
48 pinctrl: pin-controller {
49 #address-cells = <1>;
50 #size-cells = <1>;
52 interrupt-parent = <&exti>;
54 pins-are-numbered;
57 gpio-controller;
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dstm32mp157-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
10 pinctrl: pin-controller@50002000 {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "st,stm32mp157-pinctrl";
15 interrupt-parent = <&exti>;
17 pins-are-numbered;
20 gpio-controller;
[all …]
Dstm32f7-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
7 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
8 #include <dt-bindings/mfd/stm32f7-rcc.h>
12 pinctrl: pin-controller {
13 #address-cells = <1>;
14 #size-cells = <1>;
16 interrupt-parent = <&exti>;
18 pins-are-numbered;
21 gpio-controller;
[all …]
Dstm32f4-pinctrl.dtsi2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
44 #include <dt-bindings/mfd/stm32f4-rcc.h>
48 pinctrl: pin-controller {
49 #address-cells = <1>;
50 #size-cells = <1>;
52 interrupt-parent = <&exti>;
54 pins-are-numbered;
57 gpio-controller;
[all …]
Dstm32h743-pinctrl.dtsi2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
47 pin-controller {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "st,stm32h743-pinctrl";
52 interrupt-parent = <&exti>;
54 pins-are-numbered;
57 gpio-controller;
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx7ulp-pinctrl.txt10 Please also refer pinctrl-bindings.txt in this directory for generic pinctrl
16 - compatible: "fsl,imx7ulp-iomuxc1"
17 - reg: Should contain the base physical address and size of the iomuxc
21 - pinmux: One integers array, represents a group of pins mux setting.
29 Refer to imx7ulp-pinfunc.h in in device tree source folder for all
33 - drive-strength Integer. Controls Drive Strength
36 - drive-push-pull Bool. Enable Pin Push-pull
37 - drive-open-drain Bool. Enable Pin Open-drian
38 - slew-rate: Integer. Controls Slew Rate
41 - bias-disable: Bool. Pull disabled
[all …]
Dqcom,pmic-gpio.txt6 - compatible:
10 "qcom,pm8005-gpio"
11 "qcom,pm8018-gpio"
12 "qcom,pm8038-gpio"
13 "qcom,pm8058-gpio"
14 "qcom,pm8916-gpio"
15 "qcom,pm8917-gpio"
16 "qcom,pm8921-gpio"
17 "qcom,pm8941-gpio"
18 "qcom,pm8994-gpio"
[all …]
Dpinctrl-sx150x.txt3 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
4 ../interrupt-controller/interrupts.txt for generic information regarding
8 - compatible: should be one of :
19 - reg: The I2C slave address for this device.
21 - #gpio-cells: Should be 2. The first cell is the GPIO number and the
25 - gpio-controller: Marks the device as a GPIO controller.
28 - interrupts: Interrupt specifier for the controllers interrupt.
30 - interrupt-controller: Marks the device as a interrupt controller.
32 - semtech,probe-reset: Will trigger a reset of the GPIO expander on probe,
38 Required properties for pin configuration sub-nodes:
[all …]
Dcirrus,madera-pinctrl.txt19 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
22 - pinctrl-names : must be "default"
23 - pinctrl-0 : a phandle to the node containing the subnodes containing default
32 - groups : name of one pin group to configure. One of:
42 - function : name of function to assign to this group. One of:
45 io, dsp-gpio, irq1, irq2,
46 fll1-clk, fll1-lock, fll2-clk, fll2-lock, fll3-clk, fll3-lock,
47 fllao-clk, fllao-lock,
48 opclk, opclk-async, pwm1, pwm2, spdif,
49 asrc1-in1-lock, asrc1-in2-lock, asrc2-in1-lock, asrc2-in2-lock,
[all …]
Dst,stm32-pinctrl.txt5 also provides ability to multiplex and configure the output of various on-chip
10 - compatible: value should be one of the following:
11 "st,stm32f429-pinctrl"
12 "st,stm32f469-pinctrl"
13 "st,stm32f746-pinctrl"
14 "st,stm32f769-pinctrl"
15 "st,stm32h743-pinctrl"
16 "st,stm32mp157-pinctrl"
17 "st,stm32mp157-z-pinctrl"
18 - #address-cells: The value of this property must be 1
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/
Dst,stmfx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectonics Multi-Function eXpander (STMFX) bindings
9 description: ST Multi-Function eXpander (STMFX) is a slave controller using I2C for
15 - Amelie Delaunay <amelie.delaunay@st.com>
19 const: st,stmfx-0300
27 drive-open-drain: true
29 vdd-supply:
37 const: st,stmfx-0300-pinctrl
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dqcom,pmic-gpio.txt6 - compatible:
10 "qcom,pm8005-gpio"
11 "qcom,pm8018-gpio"
12 "qcom,pm8038-gpio"
13 "qcom,pm8058-gpio"
14 "qcom,pm8916-gpio"
15 "qcom,pm8917-gpio"
16 "qcom,pm8921-gpio"
17 "qcom,pm8941-gpio"
18 "qcom,pm8950-gpio"
[all …]
Dpincfg-node.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pincfg-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
21 bias-disable:
25 bias-high-impedance:
27 description: high impedance mode ("third-state", "floating")
29 bias-bus-hold:
33 bias-pull-up:
[all …]
Dpinctrl-sx150x.txt3 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
4 ../interrupt-controller/interrupts.txt for generic information regarding
8 - compatible: should be one of :
19 - reg: The I2C slave address for this device.
21 - #gpio-cells: Should be 2. The first cell is the GPIO number and the
25 - gpio-controller: Marks the device as a GPIO controller.
28 - interrupts: Interrupt specifier for the controllers interrupt.
30 - interrupt-controller: Marks the device as a interrupt controller.
32 - semtech,probe-reset: Will trigger a reset of the GPIO expander on probe,
38 Required properties for pin configuration sub-nodes:
[all …]
Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@st.com>
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/qcom/
Dapq8096-db820c-pmic-pins.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
6 pinctrl-names = "default";
7 pinctrl-0 = <&ls_exp_gpio_f &bt_en_gpios>;
12 output-low;
13 power-source = <2>; // PM8994_GPIO_S4, 1.8V
21 output-low;
22 power-source = <PM8994_GPIO_S4>; // 1.8V
23 qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
24 bias-pull-down;
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/nvidia/
Dtegra186-p3310.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/mfd/max77620.h>
26 stdout-path = "serial0:115200n8";
37 phy-reset-gpios = <&gpio TEGRA_MAIN_GPIO(M, 4) GPIO_ACTIVE_LOW>;
38 phy-handle = <&phy>;
39 phy-mode = "rgmii";
42 #address-cells = <1>;
43 #size-cells = <0>;
46 compatible = "ethernet-phy-ieee802.3-c22";
48 interrupt-parent = <&gpio>;
[all …]
Dtegra194-p2888.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/mfd/max77620.h>
26 stdout-path = "serial0:115200n8";
33 phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW>;
34 phy-handle = <&phy>;
35 phy-mode = "rgmii-id";
38 #address-cells = <1>;
39 #size-cells = <0>;
42 compatible = "ethernet-phy-ieee802.3-c22";
44 interrupt-parent = <&gpio>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/watchdog/
Daspeed-wdt.txt4 - compatible: must be one of:
5 - "aspeed,ast2400-wdt"
6 - "aspeed,ast2500-wdt"
7 - "aspeed,ast2600-wdt"
9 - reg: physical base address of the controller and length of memory mapped
14 - aspeed,reset-type = "cpu|soc|system|none"
16 Reset behavior - Whenever a timeout occurs the watchdog can be programmed
23 If 'aspeed,reset-type=' is not specified the default is to enable system
28 - cpu: Reset CPU on watchdog timeout
30 - soc: Reset 'System on Chip' on watchdog timeout
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/watchdog/
Daspeed-wdt.txt4 - compatible: must be one of:
5 - "aspeed,ast2400-wdt"
6 - "aspeed,ast2500-wdt"
8 - reg: physical base address of the controller and length of memory mapped
13 - aspeed,reset-type = "cpu|soc|system|none"
15 Reset behavior - Whenever a timeout occurs the watchdog can be programmed
22 If 'aspeed,reset-type=' is not specfied the default is to enable system
27 - cpu: Reset CPU on watchdog timeout
29 - soc: Reset 'System on Chip' on watchdog timeout
31 - system: Reset system on watchdog timeout
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/nvidia/
Dtegra186-p3310.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/mfd/max77620.h>
27 stdout-path = "serial0:115200n8";
38 phy-reset-gpios = <&gpio TEGRA186_MAIN_GPIO(M, 4)
40 phy-handle = <&phy>;
41 phy-mode = "rgmii";
44 #address-cells = <1>;
45 #size-cells = <0>;
48 compatible = "ethernet-phy-ieee802.3-c22";
50 interrupt-parent = <&gpio>;
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/
Dpinconf-generic.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
22 #include <linux/pinctrl/pinconf-generic.h>
26 #include "pinctrl-utils.h"
33 PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", NULL, false),
35 "input bias pull to pin specific state", NULL, false),
36 PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL, false),
37 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL, false),
38 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL, false),
[all …]

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