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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/
Darm,arch_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - enum:
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/kernel/linux/linux-4.19/drivers/clocksource/
DKconfig142 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
165 32-bit free running decrementing counters.
225 bool "Integrator-ap timer driver" if COMPILE_TEST
228 Enables support for the Integrator-ap timer.
268 available on many OMAP-like platforms.
293 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
297 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
302 bool "Support for 64-bit counters in ARC HS38 cores" if COMPILE_TEST
306 This enables 2 different 64-bit timers: RTC (for UP) and GFRC (for SMP)
324 power-of-2 divisor of the clock rate. The behaviour can also be
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Darm_arch_timer.c101 writel_relaxed(val, timer->base + CNTP_CTL); in arch_timer_reg_write()
104 writel_relaxed(val, timer->base + CNTP_TVAL); in arch_timer_reg_write()
111 writel_relaxed(val, timer->base + CNTV_CTL); in arch_timer_reg_write()
114 writel_relaxed(val, timer->base + CNTV_TVAL); in arch_timer_reg_write()
132 val = readl_relaxed(timer->base + CNTP_CTL); in arch_timer_reg_read()
135 val = readl_relaxed(timer->base + CNTP_TVAL); in arch_timer_reg_read()
142 val = readl_relaxed(timer->base + CNTV_CTL); in arch_timer_reg_read()
145 val = readl_relaxed(timer->base + CNTV_TVAL); in arch_timer_reg_read()
205 _retries--; \
238 * Theoretically the erratum should not occur more than twice in succession
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/kernel/linux/linux-4.19/Documentation/arm64/
Dsilicon-errata.txt8 so-called "errata", which can cause it to deviate from the architecture
26 a Category A erratum into a Category C erratum. These are collectively
28 cases (e.g. those cases that both require a non-secure workaround *and*
32 the erratum in question, a Kconfig entry is added under "Kernel
33 Features" -> "ARM errata workarounds via the alternatives framework".
35 CPU is detected. For less-intrusive workarounds, a Kconfig option is not
37 a way that the erratum will not be hit.
45 | Implementor | Component | Erratum ID | Kconfig |
46 +----------------+-----------------+-----------------+-----------------------------+
47 | Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 |
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/kernel/linux/linux-5.10/drivers/clocksource/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
164 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
187 32-bit free running decrementing counters.
241 bool "Integrator-AP timer driver" if COMPILE_TEST
244 Enables support for the Integrator-AP timer.
277 available on many OMAP-like platforms.
286 It has a 64-bit counter with update rate up to 1000MHz.
287 This counter is accessed via couple of 32-bit memory-mapped registers.
306 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
310 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
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Darm_arch_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
99 writel_relaxed(val, timer->base + CNTP_CTL); in arch_timer_reg_write()
102 writel_relaxed(val, timer->base + CNTP_TVAL); in arch_timer_reg_write()
109 writel_relaxed(val, timer->base + CNTV_CTL); in arch_timer_reg_write()
112 writel_relaxed(val, timer->base + CNTV_TVAL); in arch_timer_reg_write()
130 val = readl_relaxed(timer->base + CNTP_CTL); in arch_timer_reg_read()
133 val = readl_relaxed(timer->base + CNTP_TVAL); in arch_timer_reg_read()
140 val = readl_relaxed(timer->base + CNTV_CTL); in arch_timer_reg_read()
143 val = readl_relaxed(timer->base + CNTV_TVAL); in arch_timer_reg_read()
223 _retries--; \
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/kernel/linux/linux-5.10/Documentation/arm64/
Dsilicon-errata.rst10 so-called "errata", which can cause it to deviate from the architecture
30 a Category A erratum into a Category C erratum. These are collectively
32 cases (e.g. those cases that both require a non-secure workaround *and*
36 the erratum in question, a Kconfig entry is added under "Kernel
37 Features" -> "ARM errata workarounds via the alternatives framework".
39 CPU is detected. For less-intrusive workarounds, a Kconfig option is not
41 a way that the erratum will not be hit.
49 +----------------+-----------------+-----------------+-----------------------------+
50 | Implementor | Component | Erratum ID | Kconfig |
52 | Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 |
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-a64.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun8i-de2.h>
8 #include <dt-bindings/clock/sun8i-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/reset/sun50i-a64-ccu.h>
11 #include <dt-bindings/reset/sun8i-de2.h>
12 #include <dt-bindings/reset/sun8i-r-ccu.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
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