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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
13 ARM SMP cores are often associated with a GIC, providing per processor
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic.txt3 ARM SMP cores are often associated with a GIC, providing per processor
7 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
13 - compatible : should be one of:
14 "arm,arm1176jzf-devchip-gic"
15 "arm,arm11mp-gic"
16 "arm,cortex-a15-gic"
17 "arm,cortex-a7-gic"
18 "arm,cortex-a9-gic"
19 "arm,eb11mp-gic"
20 "arm,gic-400"
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/apm/
Dapm-shadowcat.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
9 compatible = "apm,xgene-shadowcat";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/apm/
Dapm-shadowcat.dtsi2 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
13 compatible = "apm,xgene-shadowcat";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <2>;
20 #size-cells = <0>;
26 enable-method = "spin-table";
27 cpu-release-addr = <0x1 0x0000fff8>;
28 next-level-cache = <&xgene_L2_0>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/broadcom/northstar2/
Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/broadcom/northstar2/
Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57", "arm,armv8";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/marvell/
Darmada-ap806.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /dts-v1/;
14 compatible = "marvell,armada-ap806";
15 #address-cells = <2>;
16 #size-cells = <2>;
26 compatible = "arm,psci-0.2";
30 reserved-memory {
31 #address-cells = <2>;
32 #size-cells = <2>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/
Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/
Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 clock-frequency = <50000000>;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 frame@2a830000 {
19 frame-number = <1>;
30 interrupt-names = "mhu_lpri_rx",
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/arm/
Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 clock-frequency = <50000000>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 frame@2a830000 {
19 frame-number = <1>;
30 interrupt-names = "mhu_lpri_rx",
[all …]
/kernel/linux/linux-4.19/drivers/irqchip/
Dirq-gic-v2m.c2 * ARM GIC v2m MSI(-X) support
19 #include <linux/dma-iommu.h>
28 #include <linux/irqchip/arm-gic.h>
51 /* APM X-Gene with GICv2m MSI_IIDR register value */
57 /* List of flags for specific v2m implementation */
72 u32 flags; /* v2m flags for specific implementation */
103 struct v2m_data *v2m = irq_data_get_irq_chip_data(data); in gicv2m_compose_msi_msg() local
104 phys_addr_t addr = v2m->res.start + V2M_MSI_SETSPI_NS; in gicv2m_compose_msi_msg()
106 msg->address_hi = upper_32_bits(addr); in gicv2m_compose_msi_msg()
107 msg->address_lo = lower_32_bits(addr); in gicv2m_compose_msi_msg()
[all …]
/kernel/linux/linux-5.10/drivers/irqchip/
Dirq-gic-v2m.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM GIC v2m MSI(-X) support
16 #include <linux/dma-iommu.h>
26 #include <linux/irqchip/arm-gic.h>
49 /* APM X-Gene with GICv2m MSI_IIDR register value */
55 /* List of flags for specific v2m implementation */
71 u32 flags; /* v2m flags for specific implementation */
100 static phys_addr_t gicv2m_get_msi_addr(struct v2m_data *v2m, int hwirq) in gicv2m_get_msi_addr() argument
102 if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) in gicv2m_get_msi_addr()
103 return v2m->res.start | ((hwirq - 32) << 3); in gicv2m_get_msi_addr()
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/amd/
Damd-seattle-soc.dtsi1 // SPDX-License-Identifier: GPL-2.0
10 interrupt-parent = <&gic0>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 gic0: interrupt-controller@e1101000 {
15 compatible = "arm,gic-400", "arm,cortex-a15-gic";
16 interrupt-controller;
17 #interrupt-cells = <3>;
18 #address-cells = <2>;
19 #size-cells = <2>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/amd/
Damd-seattle-soc.dtsi1 // SPDX-License-Identifier: GPL-2.0
10 interrupt-parent = <&gic0>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 gic0: interrupt-controller@e1101000 {
15 compatible = "arm,gic-400", "arm,cortex-a15-gic";
16 interrupt-controller;
17 #interrupt-cells = <3>;
18 #address-cells = <2>;
19 #size-cells = <2>;
[all …]