1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2016 Marvell Technology Group Ltd. 4 * 5 * Device Tree file for Marvell Armada AP806. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/dts-v1/; 11 12/ { 13 model = "Marvell Armada AP806"; 14 compatible = "marvell,armada-ap806"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 serial0 = &uart0; 20 serial1 = &uart1; 21 gpio0 = &ap_gpio; 22 spi0 = &spi0; 23 }; 24 25 psci { 26 compatible = "arm,psci-0.2"; 27 method = "smc"; 28 }; 29 30 reserved-memory { 31 #address-cells = <2>; 32 #size-cells = <2>; 33 ranges; 34 35 /* 36 * This area matches the mapping done with a 37 * mainline U-Boot, and should be updated by the 38 * bootloader. 39 */ 40 41 psci-area@4000000 { 42 reg = <0x0 0x4000000 0x0 0x200000>; 43 no-map; 44 }; 45 }; 46 47 ap806 { 48 #address-cells = <2>; 49 #size-cells = <2>; 50 compatible = "simple-bus"; 51 interrupt-parent = <&gic>; 52 ranges; 53 54 config-space@f0000000 { 55 #address-cells = <1>; 56 #size-cells = <1>; 57 compatible = "simple-bus"; 58 ranges = <0x0 0x0 0xf0000000 0x1000000>; 59 60 gic: interrupt-controller@210000 { 61 compatible = "arm,gic-400"; 62 #interrupt-cells = <3>; 63 #address-cells = <1>; 64 #size-cells = <1>; 65 ranges; 66 interrupt-controller; 67 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 68 reg = <0x210000 0x10000>, 69 <0x220000 0x20000>, 70 <0x240000 0x20000>, 71 <0x260000 0x20000>; 72 73 gic_v2m0: v2m@280000 { 74 compatible = "arm,gic-v2m-frame"; 75 msi-controller; 76 reg = <0x280000 0x1000>; 77 arm,msi-base-spi = <160>; 78 arm,msi-num-spis = <32>; 79 }; 80 gic_v2m1: v2m@290000 { 81 compatible = "arm,gic-v2m-frame"; 82 msi-controller; 83 reg = <0x290000 0x1000>; 84 arm,msi-base-spi = <192>; 85 arm,msi-num-spis = <32>; 86 }; 87 gic_v2m2: v2m@2a0000 { 88 compatible = "arm,gic-v2m-frame"; 89 msi-controller; 90 reg = <0x2a0000 0x1000>; 91 arm,msi-base-spi = <224>; 92 arm,msi-num-spis = <32>; 93 }; 94 gic_v2m3: v2m@2b0000 { 95 compatible = "arm,gic-v2m-frame"; 96 msi-controller; 97 reg = <0x2b0000 0x1000>; 98 arm,msi-base-spi = <256>; 99 arm,msi-num-spis = <32>; 100 }; 101 }; 102 103 timer { 104 compatible = "arm,armv8-timer"; 105 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 106 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 107 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 108 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 109 }; 110 111 pmu { 112 compatible = "arm,cortex-a72-pmu"; 113 interrupt-parent = <&pic>; 114 interrupts = <17>; 115 }; 116 117 odmi: odmi@300000 { 118 compatible = "marvell,odmi-controller"; 119 interrupt-controller; 120 msi-controller; 121 marvell,odmi-frames = <4>; 122 reg = <0x300000 0x4000>, 123 <0x304000 0x4000>, 124 <0x308000 0x4000>, 125 <0x30C000 0x4000>; 126 marvell,spi-base = <128>, <136>, <144>, <152>; 127 }; 128 129 gicp: gicp@3f0040 { 130 compatible = "marvell,ap806-gicp"; 131 reg = <0x3f0040 0x10>; 132 marvell,spi-ranges = <64 64>, <288 64>; 133 msi-controller; 134 }; 135 136 pic: interrupt-controller@3f0100 { 137 compatible = "marvell,armada-8k-pic"; 138 reg = <0x3f0100 0x10>; 139 #interrupt-cells = <1>; 140 interrupt-controller; 141 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 142 }; 143 144 xor@400000 { 145 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 146 reg = <0x400000 0x1000>, 147 <0x410000 0x1000>; 148 msi-parent = <&gic_v2m0>; 149 clocks = <&ap_clk 3>; 150 dma-coherent; 151 }; 152 153 xor@420000 { 154 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 155 reg = <0x420000 0x1000>, 156 <0x430000 0x1000>; 157 msi-parent = <&gic_v2m0>; 158 clocks = <&ap_clk 3>; 159 dma-coherent; 160 }; 161 162 xor@440000 { 163 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 164 reg = <0x440000 0x1000>, 165 <0x450000 0x1000>; 166 msi-parent = <&gic_v2m0>; 167 clocks = <&ap_clk 3>; 168 dma-coherent; 169 }; 170 171 xor@460000 { 172 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 173 reg = <0x460000 0x1000>, 174 <0x470000 0x1000>; 175 msi-parent = <&gic_v2m0>; 176 clocks = <&ap_clk 3>; 177 dma-coherent; 178 }; 179 180 spi0: spi@510600 { 181 compatible = "marvell,armada-380-spi"; 182 reg = <0x510600 0x50>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&ap_clk 3>; 187 status = "disabled"; 188 }; 189 190 i2c0: i2c@511000 { 191 compatible = "marvell,mv78230-i2c"; 192 reg = <0x511000 0x20>; 193 #address-cells = <1>; 194 #size-cells = <0>; 195 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 196 timeout-ms = <1000>; 197 clocks = <&ap_clk 3>; 198 status = "disabled"; 199 }; 200 201 uart0: serial@512000 { 202 compatible = "snps,dw-apb-uart"; 203 reg = <0x512000 0x100>; 204 reg-shift = <2>; 205 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 206 reg-io-width = <1>; 207 clocks = <&ap_clk 3>; 208 status = "disabled"; 209 }; 210 211 uart1: serial@512100 { 212 compatible = "snps,dw-apb-uart"; 213 reg = <0x512100 0x100>; 214 reg-shift = <2>; 215 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 216 reg-io-width = <1>; 217 clocks = <&ap_clk 3>; 218 status = "disabled"; 219 220 }; 221 222 watchdog: watchdog@610000 { 223 compatible = "arm,sbsa-gwdt"; 224 reg = <0x610000 0x1000>, <0x600000 0x1000>; 225 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 226 }; 227 228 ap_sdhci0: sdhci@6e0000 { 229 compatible = "marvell,armada-ap806-sdhci"; 230 reg = <0x6e0000 0x300>; 231 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 232 clock-names = "core"; 233 clocks = <&ap_clk 4>; 234 dma-coherent; 235 marvell,xenon-phy-slow-mode; 236 status = "disabled"; 237 }; 238 239 ap_syscon: system-controller@6f4000 { 240 compatible = "syscon", "simple-mfd"; 241 reg = <0x6f4000 0x2000>; 242 243 ap_clk: clock { 244 compatible = "marvell,ap806-clock"; 245 #clock-cells = <1>; 246 }; 247 248 ap_pinctrl: pinctrl { 249 compatible = "marvell,ap806-pinctrl"; 250 251 uart0_pins: uart0-pins { 252 marvell,pins = "mpp11", "mpp19"; 253 marvell,function = "uart0"; 254 }; 255 }; 256 257 ap_gpio: gpio@1040 { 258 compatible = "marvell,armada-8k-gpio"; 259 offset = <0x1040>; 260 ngpios = <20>; 261 gpio-controller; 262 #gpio-cells = <2>; 263 gpio-ranges = <&ap_pinctrl 0 0 20>; 264 }; 265 }; 266 267 ap_thermal: thermal@6f808c { 268 compatible = "marvell,armada-ap806-thermal"; 269 reg = <0x6f808c 0x4>, 270 <0x6f8084 0x8>; 271 }; 272 }; 273 }; 274}; 275