| /kernel/linux/linux-4.19/arch/arm64/boot/dts/arm/ |
| D | rtsm_ve-aemv8a.dts | 20 interrupt-parent = <&gic>;
81 gic: interrupt-controller@2c001000 { label
82 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
124 interrupt-map = <0 0 0 &gic 0 0 4>,
125 <0 0 1 &gic 0 1 4>,
126 <0 0 2 &gic 0 2 4>,
127 <0 0 3 &gic 0 3 4>,
128 <0 0 4 &gic 0 4 4>,
129 <0 0 5 &gic 0 5 4>,
130 <0 0 6 &gic 0 6 4>,
[all …]
|
| D | vexpress-v2f-1xv7-ca53x2.dts | 15 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 interrupt-parent = <&gic>;
68 gic: interrupt-controller@2c001000 { label
69 compatible = "arm,gic-400";
147 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
148 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
149 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
150 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
151 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
152 <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
|
| D | foundation-v8.dtsi | 15 interrupt-parent = <&gic>;
108 interrupt-map = <0 0 0 &gic 0 0 0 0 4>,
109 <0 0 1 &gic 0 0 0 1 4>,
110 <0 0 2 &gic 0 0 0 2 4>,
111 <0 0 3 &gic 0 0 0 3 4>,
112 <0 0 4 &gic 0 0 0 4 4>,
113 <0 0 5 &gic 0 0 0 5 4>,
114 <0 0 6 &gic 0 0 0 6 4>,
115 <0 0 7 &gic 0 0 0 7 4>,
116 <0 0 8 &gic 0 0 0 8 4>,
[all …]
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/ |
| D | rtsm_ve-aemv8a.dts | 13 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 interrupt-parent = <&gic>;
97 gic: interrupt-controller@2c001000 { label
98 compatible = "arm,gic-400", "arm,cortex-a15-gic";
149 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
150 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
151 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
152 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
153 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
154 <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
|
| D | vexpress-v2f-1xv7-ca53x2.dts | 15 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 interrupt-parent = <&gic>;
82 gic: interrupt-controller@2c001000 { label
83 compatible = "arm,gic-400";
161 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
162 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
163 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
164 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
165 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
166 <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
|
| D | fvp-base-revc.dts | 13 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 interrupt-parent = <&gic>;
115 gic: interrupt-controller@2f000000 { label
116 compatible = "arm,gic-v3";
131 compatible = "arm,gic-v3-its";
164 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
165 <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
166 <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
167 <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
223 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
[all …]
|
| D | foundation-v8.dtsi | 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 interrupt-parent = <&gic>;
131 interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
132 <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
133 <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
134 <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
135 <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
136 <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
137 <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
138 <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
[all …]
|
| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-gic.c | 5 * Interrupt architecture for the GIC:
40 #include <linux/irqchip/arm-gic.h>
48 #include "irq-gic-common.h"
113 * The GIC mapping of CPU interfaces does not necessarily match
115 * by the GIC itself.
311 pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16); in gic_set_type()
320 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ in gic_irq_set_vcpu_affinity()
339 struct gic_chip_data *gic = &gic_data[0]; in gic_handle_irq() local
340 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_handle_irq()
355 * is read after we've read the ACK register on the GIC. in gic_handle_irq()
[all …]
|
| /kernel/linux/linux-4.19/drivers/irqchip/ |
| D | irq-gic.c | 8 * Interrupt architecture for the GIC:
43 #include <linux/irqchip/arm-gic.h>
51 #include "irq-gic-common.h"
117 * The GIC mapping of CPU interfaces does not necessarily match
119 * by the GIC itself.
312 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ in gic_irq_set_vcpu_affinity()
348 struct gic_chip_data *gic = &gic_data[0]; in gic_handle_irq() local
349 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_handle_irq()
359 handle_domain_irq(gic->domain, irqnr, regs); in gic_handle_irq()
370 * on the GIC. in gic_handle_irq()
[all …]
|
| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | vexpress-v2p-ca5s.dts | 19 interrupt-parent = <&gic>;
107 gic: interrupt-controller@2c001000 { label
108 compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
209 interrupt-map = <0 0 0 &gic 0 0 4>,
210 <0 0 1 &gic 0 1 4>,
211 <0 0 2 &gic 0 2 4>,
212 <0 0 3 &gic 0 3 4>,
213 <0 0 4 &gic 0 4 4>,
214 <0 0 5 &gic 0 5 4>,
215 <0 0 6 &gic 0 6 4>,
[all …]
|
| D | vexpress-v2p-ca15-tc1.dts | 19 interrupt-parent = <&gic>;
80 gic: interrupt-controller@2c001000 { label
81 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
239 interrupt-map = <0 0 0 &gic 0 0 4>,
240 <0 0 1 &gic 0 1 4>,
241 <0 0 2 &gic 0 2 4>,
242 <0 0 3 &gic 0 3 4>,
243 <0 0 4 &gic 0 4 4>,
244 <0 0 5 &gic 0 5 4>,
245 <0 0 6 &gic 0 6 4>,
[all …]
|
| D | vexpress-v2p-ca9.dts | 19 interrupt-parent = <&gic>;
162 gic: interrupt-controller@1e001000 { label
163 compatible = "arm,cortex-a9-gic";
318 interrupt-map = <0 0 0 &gic 0 0 4>,
319 <0 0 1 &gic 0 1 4>,
320 <0 0 2 &gic 0 2 4>,
321 <0 0 3 &gic 0 3 4>,
322 <0 0 4 &gic 0 4 4>,
323 <0 0 5 &gic 0 5 4>,
324 <0 0 6 &gic 0 6 4>,
[all …]
|
| D | bcm5301x.dtsi | 15 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 interrupt-parent = <&gic>;
85 gic: interrupt-controller@21000 { label
86 compatible = "arm,cortex-a9-gic";
168 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
171 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
172 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
173 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
174 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
175 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
[all …]
|
| D | vexpress-v2p-ca15_a7.dts | 19 interrupt-parent = <&gic>;
130 gic: interrupt-controller@2c001000 { label
131 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
602 interrupt-map = <0 0 0 &gic 0 0 4>,
603 <0 0 1 &gic 0 1 4>,
604 <0 0 2 &gic 0 2 4>,
605 <0 0 3 &gic 0 3 4>,
606 <0 0 4 &gic 0 4 4>,
607 <0 0 5 &gic 0 5 4>,
608 <0 0 6 &gic 0 6 4>,
[all …]
|
| D | bcm53573.dtsi | 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
41 gic: interrupt-controller@1000 { label
42 compatible = "arm,cortex-a7-gic";
82 <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
85 <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
88 <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
89 <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
90 <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
91 <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | vexpress-v2p-ca5s.dts | 19 interrupt-parent = <&gic>;
121 gic: interrupt-controller@2c001000 { label
122 compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
223 interrupt-map = <0 0 0 &gic 0 0 4>,
224 <0 0 1 &gic 0 1 4>,
225 <0 0 2 &gic 0 2 4>,
226 <0 0 3 &gic 0 3 4>,
227 <0 0 4 &gic 0 4 4>,
228 <0 0 5 &gic 0 5 4>,
229 <0 0 6 &gic 0 6 4>,
[all …]
|
| D | vexpress-v2p-ca15-tc1.dts | 19 interrupt-parent = <&gic>;
94 gic: interrupt-controller@2c001000 { label
95 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
253 interrupt-map = <0 0 0 &gic 0 0 4>,
254 <0 0 1 &gic 0 1 4>,
255 <0 0 2 &gic 0 2 4>,
256 <0 0 3 &gic 0 3 4>,
257 <0 0 4 &gic 0 4 4>,
258 <0 0 5 &gic 0 5 4>,
259 <0 0 6 &gic 0 6 4>,
[all …]
|
| D | vexpress-v2p-ca9.dts | 19 interrupt-parent = <&gic>;
155 gic: interrupt-controller@1e001000 { label
156 compatible = "arm,cortex-a9-gic";
311 interrupt-map = <0 0 0 &gic 0 0 4>,
312 <0 0 1 &gic 0 1 4>,
313 <0 0 2 &gic 0 2 4>,
314 <0 0 3 &gic 0 3 4>,
315 <0 0 4 &gic 0 4 4>,
316 <0 0 5 &gic 0 5 4>,
317 <0 0 6 &gic 0 6 4>,
[all …]
|
| D | bcm5301x.dtsi | 15 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 interrupt-parent = <&gic>;
88 gic: interrupt-controller@21000 { label
89 compatible = "arm,cortex-a9-gic";
171 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
174 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
175 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
176 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
177 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
178 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
[all …]
|
| D | vexpress-v2p-ca15_a7.dts | 19 interrupt-parent = <&gic>;
149 gic: interrupt-controller@2c001000 { label
150 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
625 interrupt-map = <0 0 0 &gic 0 0 4>,
626 <0 0 1 &gic 0 1 4>,
627 <0 0 2 &gic 0 2 4>,
628 <0 0 3 &gic 0 3 4>,
629 <0 0 4 &gic 0 4 4>,
630 <0 0 5 &gic 0 5 4>,
631 <0 0 6 &gic 0 6 4>,
[all …]
|
| D | bcm53573.dtsi | 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
41 gic: interrupt-controller@1000 { label
42 compatible = "arm,cortex-a7-gic";
82 <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
85 <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
88 <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
89 <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
90 <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
91 <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
13 ARM SMP cores are often associated with a GIC, providing per processor
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
31 - arm,cortex-a7-gic
32 - arm,cortex-a5-gic
33 - arm,cortex-a9-gic
34 - arm,eb11mp-gic
35 - arm,gic-400
[all …]
|
| D | mti,gic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
14 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
16 interrupts which can be used as IPIs. The GIC also includes a free-running
21 const: mti,gic
27 file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
28 GIC interrupt number. The 3d cell encodes the interrupt flags setting up
34 Base address and length of the GIC registers space. If not present,
42 Specifies the list of CPU interrupt vectors to which the GIC may not
55 Specifies the range of GIC interrupts that are reserved for IPIs.
69 MIPS GIC includes a free-running global timer, per-CPU count/compare
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic.txt | 3 ARM SMP cores are often associated with a GIC, providing per processor
7 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
14 "arm,arm1176jzf-devchip-gic"
15 "arm,arm11mp-gic"
16 "arm,cortex-a15-gic"
17 "arm,cortex-a7-gic"
18 "arm,cortex-a9-gic"
19 "arm,eb11mp-gic"
20 "arm,gic-400"
22 "arm,tc11mp-gic"
[all …]
|
| D | mips-gic.txt | 1 MIPS Global Interrupt Controller (GIC)
3 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
5 interrupts which can be used as IPIs. The GIC also includes a free-running
9 - compatible : Should be "mti,gic".
14 See <include/dt-bindings/interrupt-controller/mips-gic.h>.
15 - The second cell is the GIC interrupt number.
21 - reg : Base address and length of the GIC registers. If not present,
24 to which the GIC may not route interrupts. Valid values are 2 - 7.
26 - mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
34 - compatible : Should be "mti,gic-timer".
[all …]
|