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/kernel/linux/linux-5.10/arch/parisc/kernel/
Dsignal32.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Signal support for 32-bit kernel builds
4 * Copyright (C) 2001 Matthew Wilcox <willy at parisc-linux.org>
5 * Copyright (C) 2006 Kyle McMartin <kyle at parisc-linux.org>
44 /* When loading 32-bit values into 64-bit registers make in restore_sigcontext32()
45 sure to clear the upper 32-bits */ in restore_sigcontext32()
50 err |= __get_user(compat_reg,&sc->sc_gr[regn]); in restore_sigcontext32()
51 regs->gr[regn] = compat_reg; in restore_sigcontext32()
52 /* Load upper half */ in restore_sigcontext32()
53 err |= __get_user(compat_regt,&rf->rf_gr[regn]); in restore_sigcontext32()
[all …]
/kernel/linux/linux-5.10/drivers/media/usb/stk1160/
Dstk1160-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * <elezegarcia--a.t--gmail.com>
10 * <rmthomas--a.t--sciolus.org>
19 /* Power-on Strapping Data */
24 #define STK1160_POSV_L_ACDOUT BIT(3)
25 #define STK1160_POSV_L_ACSYNC BIT(2)
30 * with bit #7 (0x?? OR 0x80 to activate).
39 * Bit 0 - Horizontal Decimation Control
42 * Bit 1 - Decimates Half or More Column
43 * 0 Decimates less than half from original column,
[all …]
/kernel/linux/linux-4.19/arch/parisc/kernel/
Dsignal32.c1 /* Signal support for 32-bit kernel builds
3 * Copyright (C) 2001 Matthew Wilcox <willy at parisc-linux.org>
4 * Copyright (C) 2006 Kyle McMartin <kyle at parisc-linux.org>
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
58 /* When loading 32-bit values into 64-bit registers make in restore_sigcontext32()
59 sure to clear the upper 32-bits */ in restore_sigcontext32()
64 err |= __get_user(compat_reg,&sc->sc_gr[regn]); in restore_sigcontext32()
65 regs->gr[regn] = compat_reg; in restore_sigcontext32()
66 /* Load upper half */ in restore_sigcontext32()
67 err |= __get_user(compat_regt,&rf->rf_gr[regn]); in restore_sigcontext32()
[all …]
/kernel/linux/linux-4.19/drivers/media/usb/stk1160/
Dstk1160-reg.h5 * <elezegarcia--a.t--gmail.com>
9 * <rmthomas--a.t--sciolus.org>
29 /* Power-on Strapping Data */
34 #define STK1160_POSV_L_ACDOUT BIT(3)
35 #define STK1160_POSV_L_ACSYNC BIT(2)
40 * with bit #7 (0x?? OR 0x80 to activate).
49 * Bit 0 - Horizontal Decimation Control
52 * Bit 1 - Decimates Half or More Column
53 * 0 Decimates less than half from original column,
55 * 1 Decimates half or more from original column,
[all …]
/kernel/linux/linux-4.19/include/uapi/linux/dvb/
Dosd.h1 /* SPDX-License-Identifier: LGPL-2.1+ WITH Linux-syscall-note */
21 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
31 // All functions return -2 on "not open"
36 // Opens OSD with this size and bit depth
37 // returns 0 on success, -1 on DRAM allocation error, -2 on "already open"
57 // returns 0 on success, -1 on error
62 // R,G,B, and a opacity value: 0->transparent, 1..254->mix, 255->pixel
68 // returns 0 on success, -1 on error
70 // returns color number of pixel <x>,<y>, or -1
73 // returns 0 on success, -1 on clipping all pixel (no pixel drawn)
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-ixp4xx/
Dixp4xx_qmgr.c20 static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
36 int bit; in qmgr_set_irq() local
38 reg = &qmgr_regs->irqsrc[queue >> 3]; /* 8 queues per u32 */ in qmgr_set_irq()
39 bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */ in qmgr_set_irq()
40 __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), in qmgr_set_irq()
43 /* IRQ source for queues 32-63 is fixed */ in qmgr_set_irq()
57 /* ACK - it may clear any bits so don't rely on it */ in qmgr_irq1_a0()
58 __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[0]); in qmgr_irq1_a0()
60 en_bitmap = qmgr_regs->irqen[0]; in qmgr_irq1_a0()
63 en_bitmap &= ~BIT(i); in qmgr_irq1_a0()
[all …]
/kernel/linux/linux-5.10/include/uapi/linux/dvb/
Dosd.h1 /* SPDX-License-Identifier: LGPL-2.1+ WITH Linux-syscall-note */
3 * osd.h - DEPRECATED On Screen Display API
23 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 /* All functions return -2 on "not open" */
41 * Opens OSD with this size and bit depth
42 * returns 0 on success, -1 on DRAM allocation error, -2 on "already open"
72 * returns 0 on success, -1 on error
79 * R,G,B, and a opacity value: 0->transparent, 1..254->mix, 255->pixel
89 * returns 0 on success, -1 on error
92 /* returns color number of pixel <x>,<y>, or -1 */
[all …]
/kernel/linux/linux-5.10/include/soc/mscc/
Docelot_vcap.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT)
26 u16 tg_width; /* Type-group width (in bits) */
48 /* VCAP Type-Group values */
51 #define VCAP_TG_HALF 2 /* Half entry */
57 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21)
58 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20)
59 #define VCAP_CORE_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19)
63 #define VCAP_CORE_UPDATE_CTRL_UPDATE_SHOT BIT(2)
64 #define VCAP_CORE_UPDATE_CTRL_CLEAR_CACHE BIT(1)
65 #define VCAP_CORE_UPDATE_CTRL_MV_TRAFFIC_IGN BIT(0)
[all …]
/kernel/linux/linux-5.10/drivers/soc/ixp4xx/
Dixp4xx-qmgr.c1 // SPDX-License-Identifier: GPL-2.0-only
20 static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
36 __raw_writel(val, &qmgr_regs->acc[queue][0]); in qmgr_put_entry()
42 val = __raw_readl(&qmgr_regs->acc[queue][0]); in qmgr_get_entry()
54 return (__raw_readl(&qmgr_regs->stat1[queue >> 3]) in __qmgr_get_stat1()
61 return (__raw_readl(&qmgr_regs->stat2[queue >> 4]) in __qmgr_get_stat2()
66 * qmgr_stat_empty() - checks if a hardware queue is empty
69 * Returns non-zero value if the queue is empty.
78 * qmgr_stat_below_low_watermark() - checks if a queue is below low watermark
81 * Returns non-zero value if the queue is below low watermark.
[all …]
/kernel/linux/linux-4.19/arch/x86/math-emu/
Dreg_round.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 /*---------------------------------------------------------------------------+
10 | Australia. E-mail billm@suburbia.net |
20 | Return value is the tag of the answer, or-ed with FPU_Exception if |
21 | one was raised, or -1 on internal error. |
26 +---------------------------------------------------------------------------*/
28 /*---------------------------------------------------------------------------+
32 | %eax:%ebx 64 bit significand |
33 | %edx 32 bit extension of the significand |
47 | must be non-zero. |
[all …]
/kernel/linux/linux-5.10/arch/x86/math-emu/
Dreg_round.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 /*---------------------------------------------------------------------------+
10 | Australia. E-mail billm@suburbia.net |
20 | Return value is the tag of the answer, or-ed with FPU_Exception if |
21 | one was raised, or -1 on internal error. |
26 +---------------------------------------------------------------------------*/
28 /*---------------------------------------------------------------------------+
32 | %eax:%ebx 64 bit significand |
33 | %edx 32 bit extension of the significand |
47 | must be non-zero. |
[all …]
/kernel/linux/linux-5.10/arch/parisc/include/asm/
Dchecksum.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * and adds in "sum" (32-bit)
11 * returns a 32-bit number suitable for feeding into itself
17 * it's best to have buff aligned on a 32-bit boundary
34 " addib,<= -4, %2, 2f\n" in ip_fast_csum()
51 " subi -1, %0, %0\n" in ip_fast_csum()
66 /* add the swapped two 16-bit halves of sum, in csum_fold()
67 a possible carry from adding the two 16-bit halves, in csum_fold()
68 will carry from the lower half into the upper half, in csum_fold()
69 giving us the correct sum in the upper half. */ in csum_fold()
[all …]
/kernel/linux/linux-5.10/include/linux/
Dcnt32_to_63.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Extend a 32-bit counter to 63 bits
31 * cnt32_to_63 - Expand a 32-bit counter to a 63-bit counter
35 * a relatively short period making wrap-arounds rather frequent. This
36 * is a problem when implementing sched_clock() for example, where a 64-bit
37 * non-wrapping monotonic value is expected to be returned.
39 * To overcome that limitation, let's extend a 32-bit counter to 63 bits
41 * by the hardware while bits 32 to 62 are stored in memory. The top bit in
42 * memory is used to synchronize with the hardware clock half-period. When
43 * the top bit of both counters (hardware and in memory) differ then the
[all …]
/kernel/linux/linux-4.19/include/linux/
Dcnt32_to_63.h2 * Extend a 32-bit counter to 63 bits
34 * cnt32_to_63 - Expand a 32-bit counter to a 63-bit counter
38 * a relatively short period making wrap-arounds rather frequent. This
39 * is a problem when implementing sched_clock() for example, where a 64-bit
40 * non-wrapping monotonic value is expected to be returned.
42 * To overcome that limitation, let's extend a 32-bit counter to 63 bits
44 * by the hardware while bits 32 to 62 are stored in memory. The top bit in
45 * memory is used to synchronize with the hardware clock half-period. When
46 * the top bit of both counters (hardware and in memory) differ then the
51 * always be in synch with the top bit indicating to any potential concurrent
[all …]
/kernel/linux/linux-4.19/arch/parisc/include/asm/
Dchecksum.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * and adds in "sum" (32-bit)
11 * returns a 32-bit number suitable for feeding into itself
17 * it's best to have buff aligned on a 32-bit boundary
24 * Here even more important to align src and dst on a 32-bit (or even
25 * better 64-bit) boundary
48 " addib,<= -4, %2, 2f\n" in ip_fast_csum()
65 " subi -1, %0, %0\n" in ip_fast_csum()
80 /* add the swapped two 16-bit halves of sum, in csum_fold()
81 a possible carry from adding the two 16-bit halves, in csum_fold()
[all …]
/kernel/linux/linux-5.10/include/uapi/linux/
Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
63 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
64 #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
[all …]
/kernel/linux/linux-5.10/drivers/crypto/qat/qat_common/
Dadf_pf2vf_msg.h1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2 /* Copyright(c) 2015 - 2020 Intel Corporation */
7 * PF<->VF Messaging
8 * The PF has an array of 32-bit PF2VF registers, one for each VF. The
13 * The bottom half is for PF->VF messages. In particular when the first
14 * bit of this register (bit 0) gets set an interrupt will be triggered
16 * The top half is for VF->PF messages. In particular when the first bit
17 * of this half of register (bit 16) gets set an interrupt will be triggered
27 * +-----------------------------------------------+
33 * Message-specific Data/Reserved
[all …]
/kernel/linux/linux-4.19/include/uapi/linux/
Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
63 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
64 #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
[all …]
/kernel/linux/linux-5.10/drivers/clk/sunxi/
Dclk-sun4i-tcon-ch1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 #include <linux/clk-provider.h>
17 #define TCON_CH1_SCLK2_GATE_BIT BIT(31)
23 #define TCON_CH1_SCLK1_GATE_BIT BIT(15)
24 #define TCON_CH1_SCLK1_HALF_BIT BIT(11)
40 spin_lock_irqsave(&tclk->lock, flags); in tcon_ch1_disable()
41 reg = readl(tclk->reg); in tcon_ch1_disable()
43 writel(reg, tclk->reg); in tcon_ch1_disable()
44 spin_unlock_irqrestore(&tclk->lock, flags); in tcon_ch1_disable()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/atheros/atlx/
Datlx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* atlx_hw.h -- common hardware definitions for Attansic network drivers
4 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
5 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
6 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
10 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
149 /* IRQ Anti-Lost Timer Initial Value Register */
228 /* MAC Half-Duplex Control Register */
246 /* Wake-On-Lan control register */
303 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
[all …]
/kernel/linux/linux-4.19/drivers/clk/sunxi/
Dclk-sun4i-tcon-ch1.c4 * Maxime Ripard <maxime.ripard@free-electrons.com>
17 #include <linux/clk-provider.h>
25 #define TCON_CH1_SCLK2_GATE_BIT BIT(31)
31 #define TCON_CH1_SCLK1_GATE_BIT BIT(15)
32 #define TCON_CH1_SCLK1_HALF_BIT BIT(11)
48 spin_lock_irqsave(&tclk->lock, flags); in tcon_ch1_disable()
49 reg = readl(tclk->reg); in tcon_ch1_disable()
51 writel(reg, tclk->reg); in tcon_ch1_disable()
52 spin_unlock_irqrestore(&tclk->lock, flags); in tcon_ch1_disable()
61 spin_lock_irqsave(&tclk->lock, flags); in tcon_ch1_enable()
[all …]
/kernel/linux/linux-5.10/drivers/mtd/spi-nor/
Dsfdp.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/mtd/spi-nor.h>
13 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
15 (((p)->parameter_table_pointer[2] << 16) | \
16 ((p)->parameter_table_pointer[1] << 8) | \
17 ((p)->parameter_table_pointer[0] << 0))
21 #define SFDP_4BAIT_ID 0xff84 /* 4-byte Address Instruction Table */
29 u8 nph; /* 0-base number of parameter headers */
38 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
42 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
[all …]
/kernel/linux/linux-4.19/Documentation/driver-api/iio/
Dtriggered-buffers.rst26 pf->timestamp = iio_get_time_ns((struct indio_dev *)p);
36 for_each_set_bit(bit, active_scan_mask, masklength)
37 buf[i++] = sensor_get_data(bit)
56 * **sensor_iio_pollfunc**, the function that will be used as top half of poll
61 * **sensor_trigger_handler**, the function that will be used as bottom half of
65 top half.
69 .. kernel-doc:: drivers/iio/buffer/industrialio-triggered-buffer.c
/kernel/linux/linux-5.10/Documentation/driver-api/iio/
Dtriggered-buffers.rst26 pf->timestamp = iio_get_time_ns((struct indio_dev *)p);
36 for_each_set_bit(bit, active_scan_mask, masklength)
37 buf[i++] = sensor_get_data(bit)
56 * **sensor_iio_pollfunc**, the function that will be used as top half of poll
61 * **sensor_trigger_handler**, the function that will be used as bottom half of
65 top half.
69 .. kernel-doc:: drivers/iio/buffer/industrialio-triggered-buffer.c
/kernel/linux/linux-4.19/drivers/net/ethernet/atheros/atlx/
Datlx.h1 /* atlx_hw.h -- common hardware definitions for Attansic network drivers
3 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
4 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
5 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
9 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
162 /* IRQ Anti-Lost Timer Initial Value Register */
241 /* MAC Half-Duplex Control Register */
259 /* Wake-On-Lan control register */
316 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
[all …]

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