| /kernel/linux/linux-4.19/arch/riscv/kernel/ |
| D | cpu.c | 18 /* Return -1 if not a valid hart */
22 u32 hart; in riscv_of_processor_hart() local
29 if (of_property_read_u32(node, "reg", &hart)) { in riscv_of_processor_hart()
30 pr_warn("Found CPU without hart ID\n"); in riscv_of_processor_hart()
33 if (hart >= NR_CPUS) { in riscv_of_processor_hart()
34 pr_info("Found hart ID %d, which is above NR_CPUs. Disabling this hart\n", hart); in riscv_of_processor_hart()
39 pr_warn("CPU with hartid=%d has no \"status\" property\n", hart); in riscv_of_processor_hart()
43 pr_info("CPU with hartid=%d has a non-okay status of \"%s\"\n", hart, status); in riscv_of_processor_hart()
48 pr_warn("CPU with hartid=%d has no \"riscv,isa\" property\n", hart); in riscv_of_processor_hart()
52 pr_warn("CPU with hartid=%d has an invalid ISA of \"%s\"\n", hart, isa); in riscv_of_processor_hart()
[all …]
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| D | smpboot.c | 53 int hart, im_okay_therefore_i_am = 0; in setup_smp() local
56 hart = riscv_of_processor_hart(dn); in setup_smp()
57 if (hart >= 0) { in setup_smp()
58 set_cpu_possible(hart, true); in setup_smp()
59 set_cpu_present(hart, true); in setup_smp()
60 if (hart == smp_processor_id()) { in setup_smp()
76 * selects the first hart to boot the kernel and causes the remainder in __cpu_up()
78 * setup by that main hart. Writing __cpu_up_stack_pointer signals to in __cpu_up()
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| D | smp.c | 122 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
125 * execution resumes on each hart.
134 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm()
137 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm()
153 * performed on this hart between setting a hart's cpumask bit in flush_icache_mm()
154 * and scheduling this MM context on that hart. Sending an SBI in flush_icache_mm()
156 * messages are sent we still need to order this hart's writes in flush_icache_mm()
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| D | head.S | 41 /* Pick one hart to run the main boot sequence */
47 /* Save hart ID and DTB physical address */
130 * This hart didn't win the lottery, so we wait for the winning hart to
149 /* We lack SMP support or have too many harts, so park this hart */
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| /kernel/linux/linux-5.10/arch/riscv/kernel/ |
| D | cpu.c | 12 * Returns the hart ID of the given device tree node, or -ENODEV if the node
13 * isn't an enabled and valid RISC-V hart node.
18 u32 hart; in riscv_of_processor_hartid() local
25 if (of_property_read_u32(node, "reg", &hart)) { in riscv_of_processor_hartid()
26 pr_warn("Found CPU without hart ID\n"); in riscv_of_processor_hartid()
31 pr_info("CPU with hartid=%d is not available\n", hart); in riscv_of_processor_hartid()
36 pr_warn("CPU with hartid=%d has no \"riscv,isa\" property\n", hart); in riscv_of_processor_hartid()
40 pr_warn("CPU with hartid=%d has an invalid ISA of \"%s\"\n", hart, isa); in riscv_of_processor_hartid()
44 return hart; in riscv_of_processor_hartid()
48 * Find hart ID of the CPU DT node under which given DT node falls.
[all …]
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| D | smpboot.c | 68 int hart; in setup_smp() local
75 hart = riscv_of_processor_hartid(dn); in setup_smp()
76 if (hart < 0) in setup_smp()
79 if (hart == cpuid_to_hartid_map(0)) { in setup_smp()
86 cpuid, hart); in setup_smp()
90 cpuid_to_hartid_map(cpuid) = hart; in setup_smp()
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| D | head.S | 180 /* We lack SMP support or have too many harts, so park this hart */
241 /* Pick one hart to run the main boot sequence */
257 /* Save hart ID and DTB physical address */
298 * This hart didn't win the lottery, so we wait for the winning hart to
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| /kernel/linux/linux-5.10/arch/riscv/mm/ |
| D | cacheflush.c | 33 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
36 * execution resumes on each hart.
45 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm()
48 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm()
62 * performed on this hart between setting a hart's cpumask bit in flush_icache_mm()
63 * and scheduling this MM context on that hart. Sending an SBI in flush_icache_mm()
65 * messages are sent we still need to order this hart's writes in flush_icache_mm()
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| D | context.c | 17 * behavior in a common case (a bunch of single-hart processes on a many-hart
20 * cache flush to be performed before execution resumes on each hart. This
22 * refers to the current hart.
33 * Ensure the remote hart's writes are visible to this hart. in flush_icache_deferred()
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| /kernel/linux/linux-4.19/arch/riscv/include/asm/ |
| D | mmu_context.h | 47 * behavior in a common case (a bunch of single-hart processes on a many-hart
50 * cache flush to be performed before execution resumes on each hart. This
52 * refers to the current hart.
63 * Ensure the remote hart's writes are visible to this hart. in flush_icache_deferred()
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/riscv/ |
| D | cpus.txt | 22 * hart: A hardware execution context, which contains all the state mandated by
56 Description: Describes a hart context
67 Definition: The hart ID of this CPU node
83 Definition: Contains the RISC-V ISA string of this hart. These
89 This system contains two harts: a hart marked as disabled that's used for
90 low-level system tasks and should be ignored by Linux, and a second hart that
142 Example: Spike ISA Simulator with 1 Hart
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
7 Every interrupt is ultimately routed through a hart's HLIC before it
8 interrupts that hart.
40 definition of the hart whose CSRs control these local interrupts.
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| D | sifive,plic-1.0.0.txt | 7 hart contexts in the system, via the external interrupt source in each hart.
9 A hart context is a privilege mode in a hardware execution thread. For example,
11 privilege modes per hart; machine mode and supervisor mode.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
7 Every interrupt is ultimately routed through a hart's HLIC before it
8 interrupts that hart.
40 definition of the hart whose CSRs control these local interrupts.
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| D | sifive,plic-1.0.0.yaml | 14 hart contexts in the system, via the external interrupt source in each hart.
16 A hart context is a privilege mode in a hardware execution thread. For example,
18 privilege modes per hart; machine mode and supervisor mode.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 17 hart: A hardware execution context, which contains all the state
39 Identifies that the hart uses the RISC-V instruction set
40 and identifies the type of the hart.
45 hart. These values originate from the RISC-V Privileged
57 supported by the hart. These are documented in the RISC-V
145 // Example 2: Spike ISA Simulator with 1 Hart
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| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-riscv-intc.c | 48 * on the local hart, these functions can only be called on the hart that
102 pr_warn("unable to find hart id for %pOF\n", node); in riscv_intc_init()
107 * The DT will have one INTC DT node under each CPU (or HART) in riscv_intc_init()
110 * for the INTC DT node belonging to boot CPU (or boot HART). in riscv_intc_init()
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| /kernel/linux/linux-5.10/arch/csky/abiv2/ |
| D | cacheflush.c | 40 * Ensure the remote hart's writes are visible to this hart. in flush_icache_deferred()
64 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm_range()
68 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm_range()
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| /kernel/linux/linux-4.19/drivers/irqchip/ |
| D | irq-sifive-plic.c | 41 * Each hart context has a vector of interrupt enable bits associated with it.
48 * Each hart context has a set of control registers associated with it. Right
49 * now there's only two: a source priority threshold over which the hart will
172 * Walk up the DT tree until we find an active RISC-V core (HART) node and
234 pr_warn("failed to parse hart ID for context %d.\n", i); in plic_init()
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| /kernel/linux/linux-4.19/drivers/clocksource/ |
| D | riscv_timer.c | 14 * All RISC-V systems have a timer attached to every hart. These timers can be
22 * operations on the current hart. There is guaranteed to be exactly one timer
23 * per hart on all RISC-V systems.
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| /kernel/linux/linux-4.19/arch/riscv/include/uapi/asm/ |
| D | syscalls.h | 16 * kernel might schedule a process on another hart. There is no way for
18 * thread->hart mappings), so we've defined a RISC-V specific system call to
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| /kernel/linux/linux-5.10/tools/testing/selftests/futex/ |
| D | run.sh | 13 # Darren Hart <dvhart@linux.intel.com>
16 # 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
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| /kernel/linux/linux-5.10/tools/arch/riscv/include/uapi/asm/ |
| D | unistd.h | 29 * kernel might schedule a process on another hart. There is no way for
31 * thread->hart mappings), so we've defined a RISC-V specific system call to
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| /kernel/linux/linux-5.10/arch/riscv/include/uapi/asm/ |
| D | unistd.h | 31 * kernel might schedule a process on another hart. There is no way for
33 * thread->hart mappings), so we've defined a RISC-V specific system call to
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| /kernel/linux/linux-4.19/tools/testing/selftests/futex/ |
| D | run.sh | 17 # Darren Hart <dvhart@linux.intel.com>
20 # 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
|