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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dcalxeda.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/calxeda.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Device Tree Clock bindings for Calxeda highbank platform
13 "hb-sregs" node.
16 - Andre Przywara <andre.przywara@arm.com>
19 "#clock-cells":
24 - calxeda,hb-pll-clock
25 - calxeda,hb-a9periph-clock
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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/
Dcalxeda.txt1 Device Tree Clock bindings for Calxeda highbank platform
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "calxeda,hb-pll-clock" - for a PLL clock
10 "calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the
11 A9 clock.
12 "calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock.
13 "calxeda,hb-emmc-clock" - Divided clock for MMC/SD controller.
14 - reg : shall be the control register offset from SYSREGs base for the clock.
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Decx-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
20 #address-cells = <1>;
21 #size-cells = <1>;
22 compatible = "simple-bus";
23 interrupt-parent = <&intc>;
26 compatible = "calxeda,hb-ahci";
29 dma-coherent;
30 calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
33 calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>,
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Decx-common.dtsi2 * Copyright 2011-2012 Calxeda, Inc.
31 #address-cells = <1>;
32 #size-cells = <1>;
33 compatible = "simple-bus";
34 interrupt-parent = <&intc>;
37 compatible = "calxeda,hb-ahci";
40 dma-coherent;
41 calxeda,port-phys = <&combophy5 0 &combophy0 0
44 calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
45 calxeda,led-order = <4 0 1 2 3>;
[all …]
/kernel/linux/linux-5.10/drivers/clk/
Dclk-highbank.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
9 #include <linux/clk-provider.h>
49 reg = readl(hbclk->reg); in clk_pll_prepare()
51 writel(reg, hbclk->reg); in clk_pll_prepare()
53 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0) in clk_pll_prepare()
55 while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0) in clk_pll_prepare()
66 reg = readl(hbclk->reg); in clk_pll_unprepare()
68 writel(reg, hbclk->reg); in clk_pll_unprepare()
76 reg = readl(hbclk->reg); in clk_pll_enable()
[all …]
/kernel/linux/linux-4.19/drivers/clk/
Dclk-highbank.c2 * Copyright 2011-2012 Calxeda, Inc.
21 #include <linux/clk-provider.h>
61 reg = readl(hbclk->reg); in clk_pll_prepare()
63 writel(reg, hbclk->reg); in clk_pll_prepare()
65 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0) in clk_pll_prepare()
67 while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0) in clk_pll_prepare()
78 reg = readl(hbclk->reg); in clk_pll_unprepare()
80 writel(reg, hbclk->reg); in clk_pll_unprepare()
88 reg = readl(hbclk->reg); in clk_pll_enable()
90 writel(reg, hbclk->reg); in clk_pll_enable()
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