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/kernel/linux/linux-4.19/arch/mips/boot/dts/ingenic/
Djz4780.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/jz4780-cgu.h>
3 #include <dt-bindings/dma/jz4780-dma.h>
6 #address-cells = <1>;
7 #size-cells = <1>;
8 compatible = "ingenic,jz4780";
10 cpuintc: interrupt-controller {
11 #address-cells = <0>;
12 #interrupt-cells = <1>;
13 interrupt-controller;
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/ingenic/
Djz4780.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/jz4780-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
4 #include <dt-bindings/dma/jz4780-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "ingenic,jz4780";
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
[all …]
Dx1830.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/x1830-cgu.h>
4 #include <dt-bindings/dma/x1830-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
21 clock-names = "cpu";
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Dx1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/x1000-cgu.h>
4 #include <dt-bindings/dma/x1000-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
21 clock-names = "cpu";
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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/
Djz4740.txt4 Ingenic JZ4740/JZ4780 SoCs. These are in addition to the core MMC properties
8 - compatible: Should be one of the following:
9 - "ingenic,jz4740-mmc" for the JZ4740
10 - "ingenic,jz4780-mmc" for the JZ4780
11 - reg: Should contain the MMC controller registers location and length.
12 - interrupts: Should contain the interrupt specifier of the MMC controller.
13 - clocks: Clock for the MMC controller.
16 - dmas: List of DMA specifiers with the controller specific format
17 as described in the generic DMA client binding. A tx and rx
19 - dma-names: RX and TX DMA request names.
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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/dma/
Djz4780-dma.txt1 * Ingenic JZ4780 DMA Controller
5 - compatible: Should be "ingenic,jz4780-dma"
6 - reg: Should contain the DMA controller registers location and length.
7 - interrupts: Should contain the interrupt specifier of the DMA controller.
8 - clocks: Should contain a clock specifier for the JZ4780 PDMA clock.
9 - #dma-cells: Must be <2>. Number of integer cells in the dmas property of
10 DMA clients (see below).
14 - ingenic,reserved-channels: Bitmask of channels to reserve for devices that
22 dma: dma@13420000 {
23 compatible = "ingenic,jz4780-dma";
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dingenic,mmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: mmc-controller.yaml#
18 - enum:
19 - ingenic,jz4740-mmc
20 - ingenic,jz4725b-mmc
21 - ingenic,jz4760-mmc
22 - ingenic,jz4780-mmc
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/
Dingenic,i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
17 pattern: "^i2c@[0-9a-f]+$"
21 - enum:
22 - ingenic,jz4770-i2c
23 - ingenic,x1000-i2c
24 - items:
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/serial/
Dingenic,uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: /schemas/serial.yaml#
17 pattern: "^serial@[0-9a-f]+$"
21 - enum:
22 - ingenic,jz4740-uart
23 - ingenic,jz4760-uart
24 - ingenic,jz4780-uart
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/
Dingenic,dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/ingenic,dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs DMA Controller DT bindings
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: "dma-controller.yaml#"
18 - ingenic,jz4740-dma
19 - ingenic,jz4725b-dma
20 - ingenic,jz4770-dma
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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/sound/
Dingenic,jz4740-i2s.txt4 - compatible : "ingenic,jz4740-i2s" or "ingenic,jz4780-i2s"
5 - reg : I2S registers location and length
6 - clocks : AIC and I2S PLL clock specifiers.
7 - clock-names: "aic" and "i2s"
8 - dmas: DMA controller phandle and DMA request line for I2S Tx and Rx channels
9 - dma-names: Must be "tx" and "rx"
14 compatible = "ingenic,jz4740-i2s";
18 clock-names = "aic", "i2s";
20 dmas = <&dma 2>, <&dma 3>;
21 dma-names = "tx", "rx";
/kernel/linux/linux-5.10/drivers/dma/
Ddma-jz4780.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Ingenic JZ4780 DMA controller
6 * Author: Alex Smith <alex@alex-smith.me.uk>
21 #include "virt-dma.h"
37 /* Per-channel registers. */
98 * struct jz4780_dma_hwdesc - descriptor structure read by the DMA controller.
178 return container_of(jzchan->vchan.chan.device, struct jz4780_dma_dev, in jz4780_dma_chan_parent()
185 return readl(jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn)); in jz4780_dma_chn_readl()
191 writel(val, jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn)); in jz4780_dma_chn_writel()
197 return readl(jzdma->ctrl_base + reg); in jz4780_dma_ctrl_readl()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 subdir-ccflags-$(CONFIG_DMADEVICES_DEBUG) := -DDEBUG
4 subdir-ccflags-$(CONFIG_DMADEVICES_VDEBUG) += -DVERBOSE_DEBUG
7 obj-$(CONFIG_DMA_ENGINE) += dmaengine.o
8 obj-$(CONFIG_DMA_VIRTUAL_CHANNELS) += virt-dma.o
9 obj-$(CONFIG_DMA_ACPI) += acpi-dma.o
10 obj-$(CONFIG_DMA_OF) += of-dma.o
13 obj-$(CONFIG_DMATEST) += dmatest.o
16 obj-$(CONFIG_ALTERA_MSGDMA) += altera-msgdma.o
17 obj-$(CONFIG_AMBA_PL08X) += amba-pl08x.o
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # DMA engine configuration
7 bool "DMA Engine support"
10 DMA engines can do asynchronous data transfers without
14 DMA Device drivers supported by the configured arch, it may
18 bool "DMA Engine debugging"
22 say N here. This enables DMA engine core and driver debugging.
25 bool "DMA Engine verbose debugging"
30 the DMA engine core and drivers.
35 comment "DMA Devices"
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Dingenic,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Cercueil <paul@crapouillou.net>
14 pattern: '^audio-controller@'
18 - enum:
19 - ingenic,jz4740-i2s
20 - ingenic,jz4760-i2s
21 - ingenic,jz4770-i2s
22 - ingenic,jz4780-i2s
[all …]
/kernel/linux/linux-4.19/drivers/dma/
Ddma-jz4780.c2 * Ingenic JZ4780 DMA controller
5 * Author: Alex Smith <alex@alex-smith.me.uk>
24 #include "virt-dma.h"
39 /* Per-channel registers. */
90 * struct jz4780_dma_hwdesc - descriptor structure read by the DMA controller.
168 return container_of(jzchan->vchan.chan.device, struct jz4780_dma_dev, in jz4780_dma_chan_parent()
175 return readl(jzdma->base + reg); in jz4780_dma_readl()
181 writel(val, jzdma->base + reg); in jz4780_dma_writel()
197 desc->desc = dma_pool_alloc(jzchan->desc_pool, GFP_NOWAIT, in jz4780_dma_desc_alloc()
198 &desc->desc_phys); in jz4780_dma_desc_alloc()
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 subdir-ccflags-$(CONFIG_DMADEVICES_DEBUG) := -DDEBUG
4 subdir-ccflags-$(CONFIG_DMADEVICES_VDEBUG) += -DVERBOSE_DEBUG
7 obj-$(CONFIG_DMA_ENGINE) += dmaengine.o
8 obj-$(CONFIG_DMA_VIRTUAL_CHANNELS) += virt-dma.o
9 obj-$(CONFIG_DMA_ACPI) += acpi-dma.o
10 obj-$(CONFIG_DMA_OF) += of-dma.o
13 obj-$(CONFIG_DMATEST) += dmatest.o
16 obj-$(CONFIG_ALTERA_MSGDMA) += altera-msgdma.o
17 obj-$(CONFIG_AMBA_PL08X) += amba-pl08x.o
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DKconfig2 # DMA engine configuration
6 bool "DMA Engine support"
9 DMA engines can do asynchronous data transfers without
13 DMA Device drivers supported by the configured arch, it may
17 bool "DMA Engine debugging"
21 say N here. This enables DMA engine core and driver debugging.
24 bool "DMA Engine verbose debugging"
29 the DMA engine core and drivers.
34 comment "DMA Devices"
72 provide DMA engine support. This includes the original ARM
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/kernel/linux/linux-4.19/drivers/mtd/nand/raw/
DKconfig20 <http://www.linux-mtd.infradead.org/doc/nand.html>.
166 This is a reimplementation of M-Systems DiskOnChip 2000,
168 as opposed to the earlier self-contained MTD device drivers.
215 data on your device (created by non-Linux tools such as M-Systems'
245 partitioning to segregate write-protected blocks. On the Treo680, the
246 first five erase blocks (256KiB each) are write-protected, followed
270 include NAND flash controllers with built-in hardware ECC
296 - PXA3xx processors (NFCv1)
297 - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2)
298 - 64-bit Aramda platforms (7k, 8k) (NFCv2)
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/kernel/linux/linux-4.19/drivers/mmc/host/
DKconfig32 This option will enable the dma to work correctly, if you are using
33 Qcom SOCs and MMC, you would probably need this option to get DMA working.
74 implements a hardware byte swapper using a 32-bit datum.
101 disabled, it will steal the MMC cards away - rendering them
206 This selects the SDHCI support for CNS3xxx System-on-Chip devices.
267 This selects the SDHCI support for SiRF System-on-Chip devices.
313 bool "DMA support on S3C SDHCI"
316 Enable DMA support on the Samsung S3C SDHCI glue. The DMA
385 MOXA provides one multi-functional card reader which can
386 be found on some embedded hardware such as UC-7112-LX.
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Djz4740_mmc.c2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
22 #include <linux/dma-mapping.h>
29 #include <linux/mmc/slot-gpio.h>
38 #include <asm/mach-jz4740/dma.h>
39 #include <asm/mach-jz4740/jz4740_mmc.h>
162 /* DMA support */
169 /* The DMA trigger level is 8 words, that is to say, the DMA read
170 * trigger is when data words in MSC_RXFIFO is >= 8 and the DMA write
179 if (host->version >= JZ_MMC_JZ4750) in jz4740_mmc_write_irq_mask()
180 return writel(val, host->base + JZ_REG_MMC_IMASK); in jz4740_mmc_write_irq_mask()
[all …]
/kernel/linux/linux-4.19/sound/soc/jz4740/
Djz4740-i2s.c2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
27 #include <linux/dma-mapping.h>
36 #include "jz4740-i2s.h"
122 return readl(i2s->base + reg); in jz4740_i2s_read()
128 writel(value, i2s->base + reg); in jz4740_i2s_write()
138 if (dai->active) in jz4740_i2s_startup()
145 ret = clk_prepare_enable(i2s->clk_i2s); in jz4740_i2s_startup()
162 if (dai->active) in jz4740_i2s_shutdown()
169 clk_disable_unprepare(i2s->clk_i2s); in jz4740_i2s_shutdown()
180 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in jz4740_i2s_trigger()
[all …]
/kernel/linux/linux-5.10/sound/soc/jz4740/
Djz4740-i2s.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
18 #include <linux/dma-mapping.h>
27 #include "jz4740-i2s.h"
116 return readl(i2s->base + reg); in jz4740_i2s_read()
122 writel(value, i2s->base + reg); in jz4740_i2s_write()
139 ret = clk_prepare_enable(i2s->clk_i2s); in jz4740_i2s_startup()
163 clk_disable_unprepare(i2s->clk_i2s); in jz4740_i2s_shutdown()
174 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in jz4740_i2s_trigger()
193 return -EINVAL; in jz4740_i2s_trigger()
[all …]
/kernel/linux/linux-5.10/drivers/mmc/host/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
33 This option will enable the dma to work correctly, if you are using
34 Qcom SOCs and MMC, you would probably need this option to get DMA working.
44 If you have a STM32 sdmmc host with internal DMA say Y here.
85 implements a hardware byte swapper using a 32-bit datum.
114 disabled, it will steal the MMC cards away - rendering them
244 This selects the SDHCI support for CNS3xxx System-on-Chip devices.
321 This selects the SDHCI support for SiRF System-on-Chip devices.
368 bool "DMA support on S3C SDHCI"
371 Enable DMA support on the Samsung S3C SDHCI glue. The DMA
[all …]
Djz4740_mmc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
13 #include <linux/dma-mapping.h>
19 #include <linux/mmc/slot-gpio.h>
130 * is in-flight. This is used via the pre_req/post_req hooks.
174 /* DMA support */
179 /* The DMA trigger level is 8 words, that is to say, the DMA read
180 * trigger is when data words in MSC_RXFIFO is >= 8 and the DMA write
189 if (host->version >= JZ_MMC_JZ4725B) in jz4740_mmc_write_irq_mask()
190 return writel(val, host->base + JZ_REG_MMC_IMASK); in jz4740_mmc_write_irq_mask()
[all …]

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