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/kernel/linux/linux-5.10/drivers/isdn/mISDN/
Dlayer1.c94 struct layer1 *l1 = fi->userdata; in l1m_debug() local
103 printk(KERN_DEBUG "%s: %pV\n", dev_name(&l1->dch->dev.dev), &vaf); in l1m_debug()
117 struct layer1 *l1 = fi->userdata; in l1_deact_cnf() local
120 if (test_bit(FLG_L1_ACTIVATING, &l1->Flags)) in l1_deact_cnf()
121 l1->dcb(l1->dch, HW_POWERUP_REQ); in l1_deact_cnf()
127 struct layer1 *l1 = fi->userdata; in l1_deact_req_s() local
130 mISDN_FsmRestartTimer(&l1->timerX, 550, EV_TIMER_DEACT, NULL, 2); in l1_deact_req_s()
131 test_and_set_bit(FLG_L1_DEACTTIMER, &l1->Flags); in l1_deact_req_s()
137 struct layer1 *l1 = fi->userdata; in l1_power_up_s() local
139 if (test_bit(FLG_L1_ACTIVATING, &l1->Flags)) { in l1_power_up_s()
[all …]
/kernel/linux/linux-4.19/drivers/isdn/mISDN/
Dlayer1.c103 struct layer1 *l1 = fi->userdata; in l1m_debug() local
112 printk(KERN_DEBUG "%s: %pV\n", dev_name(&l1->dch->dev.dev), &vaf); in l1m_debug()
126 struct layer1 *l1 = fi->userdata; in l1_deact_cnf() local
129 if (test_bit(FLG_L1_ACTIVATING, &l1->Flags)) in l1_deact_cnf()
130 l1->dcb(l1->dch, HW_POWERUP_REQ); in l1_deact_cnf()
136 struct layer1 *l1 = fi->userdata; in l1_deact_req_s() local
139 mISDN_FsmRestartTimer(&l1->timerX, 550, EV_TIMER_DEACT, NULL, 2); in l1_deact_req_s()
140 test_and_set_bit(FLG_L1_DEACTTIMER, &l1->Flags); in l1_deact_req_s()
146 struct layer1 *l1 = fi->userdata; in l1_power_up_s() local
148 if (test_bit(FLG_L1_ACTIVATING, &l1->Flags)) { in l1_power_up_s()
[all …]
/kernel/linux/linux-4.19/drivers/isdn/hisax/
Disdnl1.c146 struct IsdnCardState *cs = st->l1.hardware; in l1m_debug()
162 if (test_and_clear_bit(FLG_L1_ACTIVATING, &st->l1.Flags)) in L1activated()
163 st->l1.l1l2(st, PH_ACTIVATE | CONFIRM, NULL); in L1activated()
165 st->l1.l1l2(st, PH_ACTIVATE | INDICATION, NULL); in L1activated()
178 st->l1.l1l2(st, PH_PAUSE | CONFIRM, NULL); in L1deactivated()
179 st->l1.l1l2(st, PH_DEACTIVATE | INDICATION, NULL); in L1deactivated()
195 if (test_and_clear_bit(FLG_L1_PULL_REQ, &stptr->l1.Flags)) { in DChannel_proc_xmt()
196 stptr->l1.l1l2(stptr, PH_PULL | CONFIRM, NULL); in DChannel_proc_xmt()
211 if (test_bit(FLG_L1_ACTTIMER, &stptr->l1.Flags)) in DChannel_proc_rcv()
212 FsmEvent(&stptr->l1.l1m, EV_TIMER_ACT, NULL); in DChannel_proc_rcv()
[all …]
Dhfc4s8s_l1.c4 /* The low layer (L1) is implemented as a loadable module for usage with */
152 int l1_state; /* actual l1 state */
182 struct hfc4s8s_l1 l1[HFC_MAX_ST]; member
187 volatile u_char r_irq_statech; /* active isdn l1 status */
304 struct hfc4s8s_l1 *l1 = iface->ifc.priv; in dch_l2l1() local
311 if (!l1->enabled) { in dch_l2l1()
315 spin_lock_irqsave(&l1->lock, flags); in dch_l2l1()
316 skb_queue_tail(&l1->d_tx_queue, skb); in dch_l2l1()
317 if ((skb_queue_len(&l1->d_tx_queue) == 1) && in dch_l2l1()
318 (l1->tx_cnt <= 0)) { in dch_l2l1()
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/
Dcache.json3 …"PublicDescription": "L1 instruction cache refill. This event counts any instruction fetch which m…
6 "BriefDescription": "L1 instruction cache refill"
9 …"PublicDescription": "L1 instruction TLB refill. This event counts any refill of the instruction L…
12 "BriefDescription": "L1 instruction TLB refill"
15 …L1 data cache refill. This event counts any load or store operation or page table walk access whic…
18 "BriefDescription": "L1 data cache refill"
21 …icDescription": "L1 data cache access. This event counts any load or store operation or page table…
24 "BriefDescription": "L1 data cache access"
27 …"PublicDescription": "L1 data TLB refill. This event counts any refill of the data L1 TLB from the…
30 "BriefDescription": "L1 data TLB refill"
[all …]
/kernel/linux/linux-5.10/Documentation/networking/
Dtls-offload-layers.svg1 …l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.82812…
/kernel/linux/linux-5.10/security/selinux/ss/
Dmls_types.h30 static inline int mls_level_eq(struct mls_level *l1, struct mls_level *l2) in mls_level_eq() argument
32 return ((l1->sens == l2->sens) && in mls_level_eq()
33 ebitmap_cmp(&l1->cat, &l2->cat)); in mls_level_eq()
36 static inline int mls_level_dom(struct mls_level *l1, struct mls_level *l2) in mls_level_dom() argument
38 return ((l1->sens >= l2->sens) && in mls_level_dom()
39 ebitmap_contains(&l1->cat, &l2->cat, 0)); in mls_level_dom()
42 #define mls_level_incomp(l1, l2) \ argument
43 (!mls_level_dom((l1), (l2)) && !mls_level_dom((l2), (l1)))
45 #define mls_level_between(l1, l2, l3) \ argument
46 (mls_level_dom((l1), (l2)) && mls_level_dom((l3), (l1)))
/kernel/linux/linux-4.19/security/selinux/ss/
Dmls_types.h30 static inline int mls_level_eq(struct mls_level *l1, struct mls_level *l2) in mls_level_eq() argument
32 return ((l1->sens == l2->sens) && in mls_level_eq()
33 ebitmap_cmp(&l1->cat, &l2->cat)); in mls_level_eq()
36 static inline int mls_level_dom(struct mls_level *l1, struct mls_level *l2) in mls_level_dom() argument
38 return ((l1->sens >= l2->sens) && in mls_level_dom()
39 ebitmap_contains(&l1->cat, &l2->cat, 0)); in mls_level_dom()
42 #define mls_level_incomp(l1, l2) \ argument
43 (!mls_level_dom((l1), (l2)) && !mls_level_dom((l2), (l1)))
45 #define mls_level_between(l1, l2, l3) \ argument
46 (mls_level_dom((l1), (l2)) && mls_level_dom((l3), (l1)))
/kernel/linux/linux-5.10/arch/sparc/kernel/
Drtrap_64.S62 andn %l1, %o0, %l1
85 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
87 and %l1, %l4, %l4
88 andn %l1, %l4, %l1
96 rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
98 and %l1, %l4, %l4
99 andn %l1, %l4, %l1
115 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
118 and %l1, %l4, %l4
119 andn %l1, %l4, %l1
[all …]
/kernel/linux/linux-4.19/arch/sparc/kernel/
Drtrap_64.S62 andn %l1, %o0, %l1
85 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
87 and %l1, %l4, %l4
88 andn %l1, %l4, %l1
96 rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
98 and %l1, %l4, %l4
99 andn %l1, %l4, %l1
115 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
118 and %l1, %l4, %l4
119 andn %l1, %l4, %l1
[all …]
/kernel/linux/linux-4.19/arch/c6x/lib/
Dcsum_64plus.S54 || ADD .L1 A16,A9,A9
67 || MVK .L1 1,A2
77 ADD .L1 A16,A9,A9
80 || ADD .L1 A8,A9,A9
87 ZERO .L1 A7
119 || ZERO .L1 A7
207 || ADD .L1 A3,A5,A5
297 MV .L1 A0,A3
314 MVK .L1 2,A0
315 AND .L1 A4,A0,A0
[all …]
/kernel/linux/linux-5.10/arch/c6x/lib/
Dcsum_64plus.S50 || ADD .L1 A16,A9,A9
63 || MVK .L1 1,A2
73 ADD .L1 A16,A9,A9
76 || ADD .L1 A8,A9,A9
83 ZERO .L1 A7
115 || ZERO .L1 A7
202 || ADD .L1 A3,A5,A5
292 MV .L1 A0,A3
309 MVK .L1 2,A0
310 AND .L1 A4,A0,A0
[all …]
/kernel/linux/linux-5.10/Documentation/virt/kvm/
Drunning-nested-guests.rst17 | L1 (Guest Hypervisor) |
31 - L1 – level-1 guest; a VM running on L0; also called the "guest
34 - L2 – level-2 guest; a VM running on L1, this is the "nested guest"
43 metal, running the LPAR hypervisor), L1 (host hypervisor), L2
47 L1, and L2) for all architectures; and will largely focus on
146 able to start an L1 guest with::
173 2. The guest hypervisor (L1) must be provided with the ``sie`` CPU
177 3. Now the KVM module can be loaded in the L1 (guest hypervisor)::
185 Migrating an L1 guest, with a *live* nested guest in it, to another
189 On AMD systems, once an L1 guest has started an L2 guest, the L1 guest
[all …]
/kernel/linux/linux-5.10/arch/c6x/include/uapi/asm/
Dswab.h15 asm("swap4 .l1 %0,%0\n" : "+a"(val)); in __c6x_swab16()
21 asm("swap4 .l1 %0,%0\n" in __c6x_swab32()
22 "swap2 .l1 %0,%0\n" in __c6x_swab32()
30 "|| swap2 .l1 %P0,%p0\n" in __c6x_swab64()
31 " swap4 .l1 %p0,%p0\n" in __c6x_swab64()
32 " swap4 .l1 %P0,%P0\n" in __c6x_swab64()
39 asm("swap2 .l1 %0,%0\n" : "+a"(val)); in __c6x_swahw32()
45 asm("swap4 .l1 %0,%0\n" : "+a"(val)); in __c6x_swahb32()
/kernel/linux/linux-4.19/arch/c6x/include/uapi/asm/
Dswab.h15 asm("swap4 .l1 %0,%0\n" : "+a"(val)); in __c6x_swab16()
21 asm("swap4 .l1 %0,%0\n" in __c6x_swab32()
22 "swap2 .l1 %0,%0\n" in __c6x_swab32()
30 "|| swap2 .l1 %P0,%p0\n" in __c6x_swab64()
31 " swap4 .l1 %p0,%p0\n" in __c6x_swab64()
32 " swap4 .l1 %P0,%P0\n" in __c6x_swab64()
39 asm("swap2 .l1 %0,%0\n" : "+a"(val)); in __c6x_swahw32()
45 asm("swap4 .l1 %0,%0\n" : "+a"(val)); in __c6x_swahb32()
/kernel/linux/linux-4.19/arch/powerpc/include/asm/
Dvdso_datapage.h73 __u32 dcache_size; /* L1 d-cache size 0x60 */
74 __u32 dcache_line_size; /* L1 d-cache line size 0x64 */
75 __u32 icache_size; /* L1 i-cache size 0x68 */
76 __u32 icache_line_size; /* L1 i-cache line size 0x6C */
81 __u32 dcache_block_size; /* L1 d-cache block size */
82 __u32 icache_block_size; /* L1 i-cache block size */
83 __u32 dcache_log_block_size; /* L1 d-cache log block size */
84 __u32 icache_log_block_size; /* L1 i-cache log block size */
113 __u32 dcache_block_size; /* L1 d-cache block size */
114 __u32 icache_block_size; /* L1 i-cache block size */
[all …]
Dsecurity_features.h45 // The L1-D cache can be flushed with ori r30,r30,0
48 // The L1-D cache can be flushed with mtspr 882,r0 (aka SPRN_TRIG2)
57 // Entries in L1-D are private to a SMT thread
69 // The L1-D cache should be flushed on MSR[HV] 1->0 transition (hypervisor to guest)
72 // The L1-D cache should be flushed on MSR[PR] 0->1 transition (kernel to userspace)
87 // The L1-D cache should be flushed when entering the kernel
90 // The L1-D cache should be flushed after user accesses from the kernel
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/amdzen2/
Drecommended.json12 "BriefDescription": "All L1 Data Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
110 "BriefDescription": "L1 Instruction Cache (32B) Fetch Miss Ratio",
117 "BriefDescription": "L1 ITLB Misses",
130 "BriefDescription": "L1 DTLB Misses",
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/amdzen1/
Drecommended.json12 "BriefDescription": "All L1 Data Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
110 "BriefDescription": "L1 Instruction Cache (32B) Fetch Miss Ratio",
117 "BriefDescription": "L1 ITLB Misses",
130 "BriefDescription": "L1 DTLB Misses",
/kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/
Dsdm660.dtsi49 L1_I_100: l1-icache {
52 L1_D_100: l1-dcache {
64 L1_I_101: l1-icache {
67 L1_D_101: l1-dcache {
79 L1_I_102: l1-icache {
82 L1_D_102: l1-dcache {
94 L1_I_103: l1-icache {
97 L1_D_103: l1-dcache {
113 L1_I_0: l1-icache {
116 L1_D_0: l1-dcache {
[all …]
/kernel/linux/linux-5.10/arch/sparc/lib/
Dxor.S370 ldda [%i1 + 0x30] %asi, %l0 /* %l0/%l1 = src + 0x30 */
390 xor %l3, %l1, %l3
418 ldda [%l7 + 0x10] %asi, %l0 /* %l0/%l1 = src2 + 0x10 */
431 xor %l1, %i5, %l1
433 xor %o3, %l1, %o3
437 ldda [%l7 + 0x30] %asi, %l0 /* %l0/%l1 = src2 + 0x30 */
449 xor %l1, %i5, %l1
451 xor %o3, %l1, %o3
482 ldda [%i0 + 0x00] %asi, %l0 /* %l0/%l1 = dest + 0x00 */
490 xor %l1, %g3, %l1
[all …]
/kernel/linux/linux-4.19/arch/sparc/lib/
Dxor.S370 ldda [%i1 + 0x30] %asi, %l0 /* %l0/%l1 = src + 0x30 */
390 xor %l3, %l1, %l3
418 ldda [%l7 + 0x10] %asi, %l0 /* %l0/%l1 = src2 + 0x10 */
431 xor %l1, %i5, %l1
433 xor %o3, %l1, %o3
437 ldda [%l7 + 0x30] %asi, %l0 /* %l0/%l1 = src2 + 0x30 */
449 xor %l1, %i5, %l1
451 xor %o3, %l1, %o3
482 ldda [%i0 + 0x00] %asi, %l0 /* %l0/%l1 = dest + 0x00 */
490 xor %l1, %g3, %l1
[all …]
/kernel/linux/linux-5.10/drivers/pci/pcie/
Daspm.c3 * Enable PCIe link L0s/L1 state and Clock Power Management
31 #define ASPM_STATE_L1 (4) /* L1 state */
32 #define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
33 #define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
34 #define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */
35 #define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */
46 u32 l1; /* L1 latency (nsec) */ member
115 /* Enable ASPM L0s/L1 */ in policy_to_aspm_state()
320 /* Convert L1 latency encoding to ns */
330 /* Convert L1 acceptable latency encoding to ns */
[all …]
/kernel/linux/linux-4.19/drivers/pci/pcie/
Daspm.c3 * Enable PCIe link L0s/L1 state and Clock Power Management
32 #define ASPM_STATE_L1 (4) /* L1 state */
33 #define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
34 #define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
35 #define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */
36 #define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */
47 u32 l1; /* L1 latency (nsec) */ member
81 /* L1 PM Substate info */
126 /* Enable ASPM L0s/L1 */ in policy_to_aspm_state()
331 /* Convert L1 latency encoding to ns */
[all …]
/kernel/linux/linux-5.10/arch/powerpc/include/asm/
Dsecurity_features.h45 // The L1-D cache can be flushed with ori r30,r30,0
48 // The L1-D cache can be flushed with mtspr 882,r0 (aka SPRN_TRIG2)
57 // Entries in L1-D are private to a SMT thread
71 // The L1-D cache should be flushed on MSR[HV] 1->0 transition (hypervisor to guest)
74 // The L1-D cache should be flushed on MSR[PR] 0->1 transition (kernel to userspace)
89 // The L1-D cache should be flushed when entering the kernel
92 // The L1-D cache should be flushed after user accesses from the kernel

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