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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/
Damlogic,gxbb-aoclkc.txt1 * Amlogic GXBB AO Clock and Reset Unit
3 The Amlogic GXBB AO clock controller generates and supplies clock to various
4 controllers within the Always-On part of the SoC.
8 - compatible: value should be different for each SoC family as :
9 - GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
10 - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
11 - GXM (S912) : "amlogic,meson-gxm-aoclkc"
12 - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
13 followed by the common "amlogic,meson-gx-aoclkc"
15 - #clock-cells: should be 1.
[all …]
Damlogic,gxbb-clkc.txt1 * Amlogic GXBB Clock and Reset Unit
3 The Amlogic GXBB clock controller generates and supplies clock to various
8 - compatible: should be:
9 "amlogic,gxbb-clkc" for GXBB SoC,
10 "amlogic,gxl-clkc" for GXL and GXM SoC,
11 "amlogic,axg-clkc" for AXG SoC.
13 - #clock-cells: should be 1.
17 preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be
21 - compatible: "syscon", "simple-mfd, and "amlogic,meson-gx-hhi-sysctrl" or
22 "amlogic,meson-axg-hhi-sysctrl"
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Damlogic,gxbb-aoclkc.txt1 * Amlogic GXBB AO Clock and Reset Unit
3 The Amlogic GXBB AO clock controller generates and supplies clock to various
4 controllers within the Always-On part of the SoC.
8 - compatible: value should be different for each SoC family as :
9 - GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
10 - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
11 - GXM (S912) : "amlogic,meson-gxm-aoclkc"
12 - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
13 - G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc"
14 followed by the common "amlogic,meson-gx-aoclkc"
[all …]
Damlogic,gxbb-clkc.txt1 * Amlogic GXBB Clock and Reset Unit
3 The Amlogic GXBB clock controller generates and supplies clock to various
8 - compatible: should be:
9 "amlogic,gxbb-clkc" for GXBB SoC,
10 "amlogic,gxl-clkc" for GXL and GXM SoC,
11 "amlogic,axg-clkc" for AXG SoC.
12 "amlogic,g12a-clkc" for G12A SoC.
13 "amlogic,g12b-clkc" for G12B SoC.
14 "amlogic,sm1-clkc" for SM1 SoC.
15 - clocks : list of clock phandle, one for each entry clock-names.
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/amlogic/
Dmeson-gxbb.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-gx.dtsi"
7 #include "meson-gx-mali450.dtsi"
8 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
9 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
10 #include <dt-bindings/clock/gxbb-clkc.h>
11 #include <dt-bindings/clock/gxbb-aoclkc.h>
12 #include <dt-bindings/reset/gxbb-aoclkc.h>
15 compatible = "amlogic,meson-gxbb";
19 compatible = "amlogic,meson-gxbb-usb2-phy";
[all …]
Dmeson-gx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/power/meson-gxbb-power.h>
16 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
23 reserved-memory {
[all …]
Dmeson-gxbb-p201.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb-p20x.dtsi"
13 compatible = "amlogic,p201", "amlogic,meson-gxbb";
14 model = "Amlogic Meson GXBB P201 Development Board";
19 pinctrl-0 = <&eth_rmii_pins>;
20 pinctrl-names = "default";
21 phy-mode = "rmii";
23 snps,reset-gpio = <&gpio GPIOZ_14 0>;
24 snps,reset-delays-us = <0>, <10000>, <1000000>;
[all …]
Dmeson-gxbb-p200.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb-p20x.dtsi"
11 #include <dt-bindings/input/input.h>
14 compatible = "amlogic,p200", "amlogic,meson-gxbb";
15 model = "Amlogic Meson GXBB P200 Development Board";
17 avdd18_usb_adc: regulator-avdd18_usb_adc {
18 compatible = "regulator-fixed";
19 regulator-name = "AVDD18_USB_ADC";
20 regulator-min-microvolt = <1800000>;
[all …]
Dmeson-gxbb-kii-pro.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb-p20x.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
14 compatible = "videostrong,kii-pro", "amlogic,meson-gxbb";
18 compatible = "gpio-leds";
21 default-state = "off";
27 gpio-keys-polled {
[all …]
Dmeson-gxbb-wetek-play2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "meson-gxbb-wetek.dtsi"
10 #include <dt-bindings/input/input.h>
13 compatible = "wetek,play2", "amlogic,meson-gxbb";
17 led-wifi {
18 label = "wetek-play:wifi-status";
20 default-state = "off";
23 led-ethernet {
24 label = "wetek-play:ethernet-status";
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/amlogic/
Dmeson-gxbb.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-gx.dtsi"
7 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
8 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
9 #include <dt-bindings/clock/gxbb-clkc.h>
10 #include <dt-bindings/clock/gxbb-aoclkc.h>
11 #include <dt-bindings/reset/gxbb-aoclkc.h>
14 compatible = "amlogic,meson-gxbb";
18 compatible = "amlogic,meson-gxbb-usb2-phy";
19 #phy-cells = <0>;
[all …]
Dmeson-gx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
21 reserved-memory {
22 #address-cells = <2>;
23 #size-cells = <2>;
[all …]
Dmeson-gxbb-p201.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb-p20x.dtsi"
13 compatible = "amlogic,p201", "amlogic,meson-gxbb";
14 model = "Amlogic Meson GXBB P201 Development Board";
19 pinctrl-0 = <&eth_rmii_pins>;
20 pinctrl-names = "default";
21 phy-mode = "rmii";
23 snps,reset-gpio = <&gpio GPIOZ_14 0>;
24 snps,reset-delays-us = <0 10000 1000000>;
[all …]
Dmeson-gxbb-p200.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb-p20x.dtsi"
11 #include <dt-bindings/input/input.h>
14 compatible = "amlogic,p200", "amlogic,meson-gxbb";
15 model = "Amlogic Meson GXBB P200 Development Board";
17 avdd18_usb_adc: regulator-avdd18_usb_adc {
18 compatible = "regulator-fixed";
19 regulator-name = "AVDD18_USB_ADC";
20 regulator-min-microvolt = <1800000>;
[all …]
Dmeson-gxl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-gx.dtsi"
8 #include <dt-bindings/clock/gxbb-clkc.h>
9 #include <dt-bindings/clock/gxbb-aoclkc.h>
10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
14 compatible = "amlogic,meson-gxl";
19 compatible = "amlogic,meson-gxl-dwc3";
20 #address-cells = <2>;
21 #size-cells = <2>;
[all …]
Dmeson-gxbb-wetek-play2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "meson-gxbb-wetek.dtsi"
10 #include <dt-bindings/input/input.h>
13 compatible = "wetek,play2", "amlogic,meson-gxbb";
18 label = "wetek-play:wifi-status";
20 default-state = "off";
24 label = "wetek-play:ethernet-status";
26 default-state = "off";
30 gpio-keys-polled {
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/
Damlogic,meson-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/reset/amlogic,meson-reset.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic Meson SoC Reset Controller
11 - Neil Armstrong <narmstrong@baylibre.com>
16 - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs
17 - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
18 - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
19 - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/
Damlogic,meson-dw-hdmi.txt4 The Amlogic Meson Synopsys Designware Integration is composed of :
5 - A Synopsys DesignWare HDMI Controller IP
6 - A TOP control block controlling the Clocks and PHY
7 - A custom HDMI PHY in order to convert video to TMDS signal
30 Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare
35 - compatible: value should be different for each SoC family as :
36 - GXBB (S905) : "amlogic,meson-gxbb-dw-hdmi"
37 - GXL (S905X, S905D) : "amlogic,meson-gxl-dw-hdmi"
38 - GXM (S912) : "amlogic,meson-gxm-dw-hdmi"
39 followed by the common "amlogic,meson-gx-dw-hdmi"
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/
Damlogic,meson-gx.txt1 Amlogic SD / eMMC controller for S905/GXBB family SoCs
10 - compatible : contains one of:
11 - "amlogic,meson-gx-mmc"
12 - "amlogic,meson-gxbb-mmc"
13 - "amlogic,meson-gxl-mmc"
14 - "amlogic,meson-gxm-mmc"
15 - "amlogic,meson-axg-mmc"
16 - clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
17 - clock-names: Should contain the following:
18 "core" - Main peripheral bus clock
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Damlogic,meson-gx.txt1 Amlogic SD / eMMC controller for S905/GXBB family SoCs
10 - compatible : contains one of:
11 - "amlogic,meson-gx-mmc"
12 - "amlogic,meson-gxbb-mmc"
13 - "amlogic,meson-gxl-mmc"
14 - "amlogic,meson-gxm-mmc"
15 - "amlogic,meson-axg-mmc"
16 - clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
17 - clock-names: Should contain the following:
18 "core" - Main peripheral bus clock
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/
Damlogic,meson-dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Neil Armstrong <narmstrong@baylibre.com>
14 The Amlogic Meson Synopsys Designware Integration is composed of
15 - A Synopsys DesignWare HDMI Controller IP
16 - A TOP control block controlling the Clocks and PHY
17 - A custom HDMI PHY in order to convert video to TMDS signal
40 Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/reset/
Damlogic,meson-reset.txt1 Amlogic Meson SoC Reset Controller
4 Please also refer to reset.txt in this directory for common reset
8 - compatible: Should be "amlogic,meson8b-reset", "amlogic,meson-gxbb-reset" or
9 "amlogic,meson-axg-reset".
10 - reg: should contain the register address base
11 - #reset-cells: 1, see below
15 reset: reset-controller {
16 compatible = "amlogic,meson-gxbb-reset";
18 #reset-cells = <1>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/
Damlogic,meson-ee-pwrc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/power/amlogic,meson-ee-pwrc.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic Meson Everything-Else Power Domains
11 - Neil Armstrong <narmstrong@baylibre.com>
14 The Everything-Else Power Domains node should be the child of a syscon
17 - compatible: Should be the following:
18 "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"
26 - amlogic,meson8-pwrc
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/phy/
Dmeson8b-usb2-phy.txt1 * Amlogic Meson8, Meson8b and GXBB USB2 PHY
4 - compatible: Depending on the platform this should be one of:
5 "amlogic,meson8-usb2-phy"
6 "amlogic,meson8b-usb2-phy"
7 "amlogic,meson-gxbb-usb2-phy"
8 - reg: The base address and length of the registers
9 - #phys-cells: should be 0 (see phy-bindings.txt in this directory)
10 - clocks: phandle and clock identifier for the phy clocks
11 - clock-names: "usb_general" and "usb"
14 - resets: reference to the reset controller
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/meson/
Dmeson_vclk.c32 * - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks
33 * - HDMI Pixel Clocks generation
37 * - Genenate Pixel clocks for 2K/4K 10bit formats
44 * | | | | | |--ENCI
45 * | HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL
46 * |__________| |_________| \ | MUX |--ENCP
47 * --VCLK2-| |--VDAC
48 * |_____|--HDMI-TX
145 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0); in meson_vid_pll_set()
146 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0); in meson_vid_pll_set()
[all …]

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