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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2016 Endless Computers, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 */
6
7#include "meson-gx.dtsi"
8#include <dt-bindings/clock/gxbb-clkc.h>
9#include <dt-bindings/clock/gxbb-aoclkc.h>
10#include <dt-bindings/gpio/meson-gxl-gpio.h>
11#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
12
13/ {
14	compatible = "amlogic,meson-gxl";
15
16	soc {
17		usb0: usb@c9000000 {
18			status = "disabled";
19			compatible = "amlogic,meson-gxl-dwc3";
20			#address-cells = <2>;
21			#size-cells = <2>;
22			ranges;
23
24			clocks = <&clkc CLKID_USB>;
25			clock-names = "usb_general";
26			resets = <&reset RESET_USB_OTG>;
27			reset-names = "usb_otg";
28
29			dwc3: dwc3@c9000000 {
30				compatible = "snps,dwc3";
31				reg = <0x0 0xc9000000 0x0 0x100000>;
32				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
33				dr_mode = "host";
34				maximum-speed = "high-speed";
35				snps,dis_u2_susphy_quirk;
36				phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
37			};
38		};
39	};
40};
41
42&apb {
43	usb2_phy0: phy@78000 {
44		compatible = "amlogic,meson-gxl-usb2-phy";
45		#phy-cells = <0>;
46		reg = <0x0 0x78000 0x0 0x20>;
47		clocks = <&clkc CLKID_USB>;
48		clock-names = "phy";
49		resets = <&reset RESET_USB_OTG>;
50		reset-names = "phy";
51		status = "okay";
52	};
53
54	usb2_phy1: phy@78020 {
55		compatible = "amlogic,meson-gxl-usb2-phy";
56		#phy-cells = <0>;
57		reg = <0x0 0x78020 0x0 0x20>;
58		clocks = <&clkc CLKID_USB>;
59		clock-names = "phy";
60		resets = <&reset RESET_USB_OTG>;
61		reset-names = "phy";
62		status = "okay";
63	};
64
65	usb3_phy: phy@78080 {
66		compatible = "amlogic,meson-gxl-usb3-phy";
67		#phy-cells = <0>;
68		reg = <0x0 0x78080 0x0 0x20>;
69		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
70		clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>;
71		clock-names = "phy", "peripheral";
72		resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
73		reset-names = "phy", "peripheral";
74		status = "okay";
75	};
76};
77
78&ethmac {
79	reg = <0x0 0xc9410000 0x0 0x10000
80	       0x0 0xc8834540 0x0 0x4>;
81
82	clocks = <&clkc CLKID_ETH>,
83		 <&clkc CLKID_FCLK_DIV2>,
84		 <&clkc CLKID_MPLL2>;
85	clock-names = "stmmaceth", "clkin0", "clkin1";
86
87	mdio0: mdio {
88		#address-cells = <1>;
89		#size-cells = <0>;
90		compatible = "snps,dwmac-mdio";
91	};
92};
93
94&aobus {
95	pinctrl_aobus: pinctrl@14 {
96		compatible = "amlogic,meson-gxl-aobus-pinctrl";
97		#address-cells = <2>;
98		#size-cells = <2>;
99		ranges;
100
101		gpio_ao: bank@14 {
102			reg = <0x0 0x00014 0x0 0x8>,
103			      <0x0 0x0002c 0x0 0x4>,
104			      <0x0 0x00024 0x0 0x8>;
105			reg-names = "mux", "pull", "gpio";
106			gpio-controller;
107			#gpio-cells = <2>;
108			gpio-ranges = <&pinctrl_aobus 0 0 14>;
109		};
110
111		uart_ao_a_pins: uart_ao_a {
112			mux {
113				groups = "uart_tx_ao_a", "uart_rx_ao_a";
114				function = "uart_ao";
115			};
116		};
117
118		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
119			mux {
120				groups = "uart_cts_ao_a",
121				       "uart_rts_ao_a";
122				function = "uart_ao";
123			};
124		};
125
126		uart_ao_b_pins: uart_ao_b {
127			mux {
128				groups = "uart_tx_ao_b", "uart_rx_ao_b";
129				function = "uart_ao_b";
130			};
131		};
132
133		uart_ao_b_0_1_pins: uart_ao_b_0_1 {
134			mux {
135				groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
136				function = "uart_ao_b";
137			};
138		};
139
140		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
141			mux {
142				groups = "uart_cts_ao_b",
143				       "uart_rts_ao_b";
144				function = "uart_ao_b";
145			};
146		};
147
148		remote_input_ao_pins: remote_input_ao {
149			mux {
150				groups = "remote_input_ao";
151				function = "remote_input_ao";
152			};
153		};
154
155		i2c_ao_pins: i2c_ao {
156			mux {
157				groups = "i2c_sck_ao",
158				       "i2c_sda_ao";
159				function = "i2c_ao";
160			};
161		};
162
163		pwm_ao_a_3_pins: pwm_ao_a_3 {
164			mux {
165				groups = "pwm_ao_a_3";
166				function = "pwm_ao_a";
167			};
168		};
169
170		pwm_ao_a_8_pins: pwm_ao_a_8 {
171			mux {
172				groups = "pwm_ao_a_8";
173				function = "pwm_ao_a";
174			};
175		};
176
177		pwm_ao_b_pins: pwm_ao_b {
178			mux {
179				groups = "pwm_ao_b";
180				function = "pwm_ao_b";
181			};
182		};
183
184		pwm_ao_b_6_pins: pwm_ao_b_6 {
185			mux {
186				groups = "pwm_ao_b_6";
187				function = "pwm_ao_b";
188			};
189		};
190
191		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
192			mux {
193				groups = "i2s_out_ch23_ao";
194				function = "i2s_out_ao";
195			};
196		};
197
198		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
199			mux {
200				groups = "i2s_out_ch45_ao";
201				function = "i2s_out_ao";
202			};
203		};
204
205		spdif_out_ao_6_pins: spdif_out_ao_6 {
206			mux {
207				groups = "spdif_out_ao_6";
208				function = "spdif_out_ao";
209			};
210		};
211
212		spdif_out_ao_9_pins: spdif_out_ao_9 {
213			mux {
214				groups = "spdif_out_ao_9";
215				function = "spdif_out_ao";
216			};
217		};
218
219		ao_cec_pins: ao_cec {
220			mux {
221				groups = "ao_cec";
222				function = "cec_ao";
223			};
224		};
225
226		ee_cec_pins: ee_cec {
227			mux {
228				groups = "ee_cec";
229				function = "cec_ao";
230			};
231		};
232	};
233};
234
235&cec_AO {
236	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
237	clock-names = "core";
238};
239
240&clkc_AO {
241	compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
242};
243
244&gpio_intc {
245	compatible = "amlogic,meson-gpio-intc",
246		     "amlogic,meson-gxl-gpio-intc";
247	status = "okay";
248};
249
250&hdmi_tx {
251	compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
252	resets = <&reset RESET_HDMITX_CAPB3>,
253		 <&reset RESET_HDMI_SYSTEM_RESET>,
254		 <&reset RESET_HDMI_TX>;
255	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
256	clocks = <&clkc CLKID_HDMI_PCLK>,
257		 <&clkc CLKID_CLK81>,
258		 <&clkc CLKID_GCLK_VENCI_INT0>;
259	clock-names = "isfr", "iahb", "venci";
260};
261
262&sysctrl {
263	clkc: clock-controller {
264		compatible = "amlogic,gxl-clkc";
265		#clock-cells = <1>;
266	};
267};
268
269&hwrng {
270	clocks = <&clkc CLKID_RNG0>;
271	clock-names = "core";
272};
273
274&i2c_A {
275	clocks = <&clkc CLKID_I2C>;
276};
277
278&i2c_AO {
279	clocks = <&clkc CLKID_AO_I2C>;
280};
281
282&i2c_B {
283	clocks = <&clkc CLKID_I2C>;
284};
285
286&i2c_C {
287	clocks = <&clkc CLKID_I2C>;
288};
289
290&periphs {
291	pinctrl_periphs: pinctrl@4b0 {
292		compatible = "amlogic,meson-gxl-periphs-pinctrl";
293		#address-cells = <2>;
294		#size-cells = <2>;
295		ranges;
296
297		gpio: bank@4b0 {
298			reg = <0x0 0x004b0 0x0 0x28>,
299			      <0x0 0x004e8 0x0 0x14>,
300			      <0x0 0x00520 0x0 0x14>,
301			      <0x0 0x00430 0x0 0x40>;
302			reg-names = "mux", "pull", "pull-enable", "gpio";
303			gpio-controller;
304			#gpio-cells = <2>;
305			gpio-ranges = <&pinctrl_periphs 0 0 100>;
306		};
307
308		emmc_pins: emmc {
309			mux {
310				groups = "emmc_nand_d07",
311				       "emmc_cmd",
312				       "emmc_clk";
313				function = "emmc";
314			};
315		};
316
317		emmc_ds_pins: emmc-ds {
318			mux {
319				groups = "emmc_ds";
320				function = "emmc";
321			};
322		};
323
324		emmc_clk_gate_pins: emmc_clk_gate {
325			mux {
326				groups = "BOOT_8";
327				function = "gpio_periphs";
328			};
329			cfg-pull-down {
330				pins = "BOOT_8";
331				bias-pull-down;
332			};
333		};
334
335		nor_pins: nor {
336			mux {
337				groups = "nor_d",
338				       "nor_q",
339				       "nor_c",
340				       "nor_cs";
341				function = "nor";
342			};
343		};
344
345		spi_pins: spi-pins {
346			mux {
347				groups = "spi_miso",
348					"spi_mosi",
349					"spi_sclk";
350				function = "spi";
351			};
352		};
353
354		spi_ss0_pins: spi-ss0 {
355			mux {
356				groups = "spi_ss0";
357				function = "spi";
358			};
359		};
360
361		sdcard_pins: sdcard {
362			mux {
363				groups = "sdcard_d0",
364				       "sdcard_d1",
365				       "sdcard_d2",
366				       "sdcard_d3",
367				       "sdcard_cmd",
368				       "sdcard_clk";
369				function = "sdcard";
370			};
371		};
372
373		sdcard_clk_gate_pins: sdcard_clk_gate {
374			mux {
375				groups = "CARD_2";
376				function = "gpio_periphs";
377			};
378			cfg-pull-down {
379				pins = "CARD_2";
380				bias-pull-down;
381			};
382		};
383
384		sdio_pins: sdio {
385			mux {
386				groups = "sdio_d0",
387				       "sdio_d1",
388				       "sdio_d2",
389				       "sdio_d3",
390				       "sdio_cmd",
391				       "sdio_clk";
392				function = "sdio";
393			};
394		};
395
396		sdio_clk_gate_pins: sdio_clk_gate {
397			mux {
398				groups = "GPIOX_4";
399				function = "gpio_periphs";
400			};
401			cfg-pull-down {
402				pins = "GPIOX_4";
403				bias-pull-down;
404			};
405		};
406
407		sdio_irq_pins: sdio_irq {
408			mux {
409				groups = "sdio_irq";
410				function = "sdio";
411			};
412		};
413
414		uart_a_pins: uart_a {
415			mux {
416				groups = "uart_tx_a",
417				       "uart_rx_a";
418				function = "uart_a";
419			};
420		};
421
422		uart_a_cts_rts_pins: uart_a_cts_rts {
423			mux {
424				groups = "uart_cts_a",
425				       "uart_rts_a";
426				function = "uart_a";
427			};
428		};
429
430		uart_b_pins: uart_b {
431			mux {
432				groups = "uart_tx_b",
433				       "uart_rx_b";
434				function = "uart_b";
435			};
436		};
437
438		uart_b_cts_rts_pins: uart_b_cts_rts {
439			mux {
440				groups = "uart_cts_b",
441				       "uart_rts_b";
442				function = "uart_b";
443			};
444		};
445
446		uart_c_pins: uart_c {
447			mux {
448				groups = "uart_tx_c",
449				       "uart_rx_c";
450				function = "uart_c";
451			};
452		};
453
454		uart_c_cts_rts_pins: uart_c_cts_rts {
455			mux {
456				groups = "uart_cts_c",
457				       "uart_rts_c";
458				function = "uart_c";
459			};
460		};
461
462		i2c_a_pins: i2c_a {
463			mux {
464				groups = "i2c_sck_a",
465				     "i2c_sda_a";
466				function = "i2c_a";
467			};
468		};
469
470		i2c_b_pins: i2c_b {
471			mux {
472				groups = "i2c_sck_b",
473				      "i2c_sda_b";
474				function = "i2c_b";
475			};
476		};
477
478		i2c_c_pins: i2c_c {
479			mux {
480				groups = "i2c_sck_c",
481				      "i2c_sda_c";
482				function = "i2c_c";
483			};
484		};
485
486		eth_pins: eth_c {
487			mux {
488				groups = "eth_mdio",
489				       "eth_mdc",
490				       "eth_clk_rx_clk",
491				       "eth_rx_dv",
492				       "eth_rxd0",
493				       "eth_rxd1",
494				       "eth_rxd2",
495				       "eth_rxd3",
496				       "eth_rgmii_tx_clk",
497				       "eth_tx_en",
498				       "eth_txd0",
499				       "eth_txd1",
500				       "eth_txd2",
501				       "eth_txd3";
502				function = "eth";
503			};
504		};
505
506		eth_link_led_pins: eth_link_led {
507			mux {
508				groups = "eth_link_led";
509				function = "eth_led";
510			};
511		};
512
513		eth_act_led_pins: eth_act_led {
514			mux {
515				groups = "eth_act_led";
516				function = "eth_led";
517			};
518		};
519
520		pwm_a_pins: pwm_a {
521			mux {
522				groups = "pwm_a";
523				function = "pwm_a";
524			};
525		};
526
527		pwm_b_pins: pwm_b {
528			mux {
529				groups = "pwm_b";
530				function = "pwm_b";
531			};
532		};
533
534		pwm_c_pins: pwm_c {
535			mux {
536				groups = "pwm_c";
537				function = "pwm_c";
538			};
539		};
540
541		pwm_d_pins: pwm_d {
542			mux {
543				groups = "pwm_d";
544				function = "pwm_d";
545			};
546		};
547
548		pwm_e_pins: pwm_e {
549			mux {
550				groups = "pwm_e";
551				function = "pwm_e";
552			};
553		};
554
555		pwm_f_clk_pins: pwm_f_clk {
556			mux {
557				groups = "pwm_f_clk";
558				function = "pwm_f";
559			};
560		};
561
562		pwm_f_x_pins: pwm_f_x {
563			mux {
564				groups = "pwm_f_x";
565				function = "pwm_f";
566			};
567		};
568
569		hdmi_hpd_pins: hdmi_hpd {
570			mux {
571				groups = "hdmi_hpd";
572				function = "hdmi_hpd";
573			};
574		};
575
576		hdmi_i2c_pins: hdmi_i2c {
577			mux {
578				groups = "hdmi_sda", "hdmi_scl";
579				function = "hdmi_i2c";
580			};
581		};
582
583		i2s_am_clk_pins: i2s_am_clk {
584			mux {
585				groups = "i2s_am_clk";
586				function = "i2s_out";
587			};
588		};
589
590		i2s_out_ao_clk_pins: i2s_out_ao_clk {
591			mux {
592				groups = "i2s_out_ao_clk";
593				function = "i2s_out";
594			};
595		};
596
597		i2s_out_lr_clk_pins: i2s_out_lr_clk {
598			mux {
599				groups = "i2s_out_lr_clk";
600				function = "i2s_out";
601			};
602		};
603
604		i2s_out_ch01_pins: i2s_out_ch01 {
605			mux {
606				groups = "i2s_out_ch01";
607				function = "i2s_out";
608			};
609		};
610		i2sout_ch23_z_pins: i2sout_ch23_z {
611			mux {
612				groups = "i2sout_ch23_z";
613				function = "i2s_out";
614			};
615		};
616
617		i2sout_ch45_z_pins: i2sout_ch45_z {
618			mux {
619				groups = "i2sout_ch45_z";
620				function = "i2s_out";
621			};
622		};
623
624		i2sout_ch67_z_pins: i2sout_ch67_z {
625			mux {
626				groups = "i2sout_ch67_z";
627				function = "i2s_out";
628			};
629		};
630
631		spdif_out_h_pins: spdif_out_ao_h {
632			mux {
633				groups = "spdif_out_h";
634				function = "spdif_out";
635			};
636		};
637	};
638
639	eth-phy-mux {
640		compatible = "mdio-mux-mmioreg", "mdio-mux";
641		#address-cells = <1>;
642		#size-cells = <0>;
643		reg = <0x0 0x55c 0x0 0x4>;
644		mux-mask = <0xffffffff>;
645		mdio-parent-bus = <&mdio0>;
646
647		internal_mdio: mdio@e40908ff {
648			reg = <0xe40908ff>;
649			#address-cells = <1>;
650			#size-cells = <0>;
651
652			internal_phy: ethernet-phy@8 {
653				compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
654				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
655				reg = <8>;
656				max-speed = <100>;
657			};
658		};
659
660		external_mdio: mdio@2009087f {
661			reg = <0x2009087f>;
662			#address-cells = <1>;
663			#size-cells = <0>;
664		};
665	};
666};
667
668&pwrc_vpu {
669	resets = <&reset RESET_VIU>,
670		 <&reset RESET_VENC>,
671		 <&reset RESET_VCBUS>,
672		 <&reset RESET_BT656>,
673		 <&reset RESET_DVIN_RESET>,
674		 <&reset RESET_RDMA>,
675		 <&reset RESET_VENCI>,
676		 <&reset RESET_VENCP>,
677		 <&reset RESET_VDAC>,
678		 <&reset RESET_VDI6>,
679		 <&reset RESET_VENCL>,
680		 <&reset RESET_VID_LOCK>;
681	clocks = <&clkc CLKID_VPU>,
682	         <&clkc CLKID_VAPB>;
683	clock-names = "vpu", "vapb";
684	/*
685	 * VPU clocking is provided by two identical clock paths
686	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
687	 * free mux to safely change frequency while running.
688	 * Same for VAPB but with a final gate after the glitch free mux.
689	 */
690	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
691			  <&clkc CLKID_VPU_0>,
692			  <&clkc CLKID_VPU>, /* Glitch free mux */
693			  <&clkc CLKID_VAPB_0_SEL>,
694			  <&clkc CLKID_VAPB_0>,
695			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
696	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
697				 <0>, /* Do Nothing */
698				 <&clkc CLKID_VPU_0>,
699				 <&clkc CLKID_FCLK_DIV4>,
700				 <0>, /* Do Nothing */
701				 <&clkc CLKID_VAPB_0>;
702	assigned-clock-rates = <0>, /* Do Nothing */
703			       <666666666>,
704			       <0>, /* Do Nothing */
705			       <0>, /* Do Nothing */
706			       <250000000>,
707			       <0>; /* Do Nothing */
708};
709
710&saradc {
711	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
712	clocks = <&xtal>,
713		 <&clkc CLKID_SAR_ADC>,
714		 <&clkc CLKID_SAR_ADC_CLK>,
715		 <&clkc CLKID_SAR_ADC_SEL>;
716	clock-names = "clkin", "core", "adc_clk", "adc_sel";
717};
718
719&sd_emmc_a {
720	clocks = <&clkc CLKID_SD_EMMC_A>,
721		 <&clkc CLKID_SD_EMMC_A_CLK0>,
722		 <&clkc CLKID_FCLK_DIV2>;
723	clock-names = "core", "clkin0", "clkin1";
724	resets = <&reset RESET_SD_EMMC_A>;
725};
726
727&sd_emmc_b {
728	clocks = <&clkc CLKID_SD_EMMC_B>,
729		 <&clkc CLKID_SD_EMMC_B_CLK0>,
730		 <&clkc CLKID_FCLK_DIV2>;
731	clock-names = "core", "clkin0", "clkin1";
732	resets = <&reset RESET_SD_EMMC_B>;
733};
734
735&sd_emmc_c {
736	clocks = <&clkc CLKID_SD_EMMC_C>,
737		 <&clkc CLKID_SD_EMMC_C_CLK0>,
738		 <&clkc CLKID_FCLK_DIV2>;
739	clock-names = "core", "clkin0", "clkin1";
740	resets = <&reset RESET_SD_EMMC_C>;
741};
742
743&spicc {
744	clocks = <&clkc CLKID_SPICC>;
745	clock-names = "core";
746	resets = <&reset RESET_PERIPHS_SPICC>;
747	num-cs = <1>;
748};
749
750&spifc {
751	clocks = <&clkc CLKID_SPI>;
752};
753
754&uart_A {
755	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
756	clock-names = "xtal", "pclk", "baud";
757};
758
759&uart_AO {
760	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
761	clock-names = "xtal", "pclk", "baud";
762};
763
764&uart_AO_B {
765	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
766	clock-names = "xtal", "pclk", "baud";
767};
768
769&uart_B {
770	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
771	clock-names = "xtal", "pclk", "baud";
772};
773
774&uart_C {
775	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
776	clock-names = "xtal", "pclk", "baud";
777};
778
779&vpu {
780	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
781	power-domains = <&pwrc_vpu>;
782};
783