| /kernel/linux/linux-5.10/include/linux/mtd/ |
| D | nand.h | 19 * @bits_per_cell: number of bits per NAND cell
27 * @ntargets: total number of targets exposed by the NAND device
67 * struct nand_pos - NAND position object
68 * @target: the NAND target/die
96 * struct nand_page_io_req - NAND I/O request object
107 * This object is used to pass per-page I/O requests to NAND sub-layers. This
109 * specific NAND layers can focus on translating these information into
135 * enum nand_ecc_engine_type - NAND ECC engine type
151 * enum nand_ecc_placement - NAND ECC bytes placement
165 * enum nand_ecc_algo - NAND ECC algorithm
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| /kernel/linux/linux-4.19/include/linux/mtd/ |
| D | nand.h | 17 * @bits_per_cell: number of bits per NAND cell
24 * @ntargets: total number of targets exposed by the NAND device
62 * struct nand_pos - NAND position object
63 * @target: the NAND target/die
81 * struct nand_page_io_req - NAND I/O request object
91 * This object is used to pass per-page I/O requests to NAND sub-layers. This
93 * specific NAND layers can focus on translating these information into
114 * struct nand_ecc_req - NAND ECC requirements
136 * struct nand_ops - NAND operations
138 * erasing, this has been taken care of by the generic NAND layer
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| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/ |
| D | Kconfig | 6 bool "NAND ECC Smart Media byte order"
14 tristate "Raw/Parallel NAND Device Support"
20 NAND flash devices. For further information see
21 <http://www.linux-mtd.infradead.org/doc/nand.html>.
32 ECC codes. They are used with NAND devices requiring more than 1 bit
35 comment "Raw/parallel NAND flash controllers"
41 tristate "Denali NAND controller on Intel Moorestown"
45 Enable the driver for NAND flash on Intel Moorestown, using the
46 Denali NAND controller core.
49 tristate "Denali NAND controller as a DT device"
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| D | nand_ids.c | 25 * Some incompatible NAND chips share device ID's and so must be
58 LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
59 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
60 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS),
61 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xD6, 8, SZ_8K, SP_OPTIONS),
62 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xE6, 8, SZ_8K, SP_OPTIONS),
64 LEGACY_ID_NAND("NAND 16MiB 1,8V 8-bit", 0x33, 16, SZ_16K, SP_OPTIONS),
65 LEGACY_ID_NAND("NAND 16MiB 3,3V 8-bit", 0x73, 16, SZ_16K, SP_OPTIONS),
66 LEGACY_ID_NAND("NAND 16MiB 1,8V 16-bit", 0x43, 16, SZ_16K, SP_OPTIONS16),
67 LEGACY_ID_NAND("NAND 16MiB 3,3V 16-bit", 0x53, 16, SZ_16K, SP_OPTIONS16),
[all …]
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| D | meson_nand.c | 3 * Amlogic Meson Nand Flash Controller Driver
91 /* nand flash controller delay 3 ns */
109 struct nand_chip nand; member
217 static struct meson_nfc_nand_chip *to_meson_nand(struct nand_chip *nand) in to_meson_nand() argument
219 return container_of(nand, struct meson_nfc_nand_chip, nand); in to_meson_nand()
222 static void meson_nfc_select_chip(struct nand_chip *nand, int chip) in meson_nfc_select_chip() argument
224 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); in meson_nfc_select_chip()
225 struct meson_nfc *nfc = nand_get_controller_data(nand); in meson_nfc_select_chip()
265 static void meson_nfc_cmd_access(struct nand_chip *nand, int raw, bool dir, in meson_nfc_cmd_access() argument
268 struct mtd_info *mtd = nand_to_mtd(nand); in meson_nfc_cmd_access()
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| D | sunxi_nand.c | 161 * struct sunxi_nand_chip_sel - stores information related to NAND Chip Select
163 * @cs: the NAND CS id used to communicate with a NAND Chip
181 * struct sunxi_nand_chip - stores NAND chip device related information
183 * @node: used to store NAND chips into a list
184 * @nand: base NAND chip structure
185 * @clk_rate: clk_rate required for this NAND chip
186 * @timing_cfg: TIMING_CFG register value for this NAND chip
187 * @timing_ctl: TIMING_CTL register value for this NAND chip
188 * @nsels: number of CS lines required by the NAND chip
193 struct nand_chip nand; member
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| /kernel/linux/linux-5.10/drivers/mtd/nand/ |
| D | core.c | 10 #define pr_fmt(fmt) "nand: " fmt
13 #include <linux/mtd/nand.h>
17 * @nand: NAND device
22 bool nanddev_isbad(struct nand_device *nand, const struct nand_pos *pos) in nanddev_isbad() argument
24 if (nanddev_bbt_is_initialized(nand)) { in nanddev_isbad()
28 entry = nanddev_bbt_pos_to_entry(nand, pos); in nanddev_isbad()
29 status = nanddev_bbt_get_block_status(nand, entry); in nanddev_isbad()
32 if (nand->ops->isbad(nand, pos)) in nanddev_isbad()
37 nanddev_bbt_set_block_status(nand, entry, status); in nanddev_isbad()
47 return nand->ops->isbad(nand, pos); in nanddev_isbad()
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| /kernel/linux/linux-4.19/drivers/mtd/nand/ |
| D | core.c | 10 #define pr_fmt(fmt) "nand: " fmt
13 #include <linux/mtd/nand.h>
17 * @nand: NAND device
22 bool nanddev_isbad(struct nand_device *nand, const struct nand_pos *pos) in nanddev_isbad() argument
24 if (nanddev_bbt_is_initialized(nand)) { in nanddev_isbad()
28 entry = nanddev_bbt_pos_to_entry(nand, pos); in nanddev_isbad()
29 status = nanddev_bbt_get_block_status(nand, entry); in nanddev_isbad()
32 if (nand->ops->isbad(nand, pos)) in nanddev_isbad()
37 nanddev_bbt_set_block_status(nand, entry, status); in nanddev_isbad()
47 return nand->ops->isbad(nand, pos); in nanddev_isbad()
[all …]
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| /kernel/linux/linux-4.19/drivers/mtd/nand/raw/ |
| D | Kconfig | 5 bool "NAND ECC Smart Media byte order"
14 tristate "Raw/Parallel NAND Device Support"
19 NAND flash devices. For further information see
20 <http://www.linux-mtd.infradead.org/doc/nand.html>.
36 ECC codes. They are used with NAND devices requiring more than 1 bit
47 tristate "Support Denali NAND controller on Intel Moorestown"
51 Enable the driver for NAND flash on Intel Moorestown, using the
52 Denali NAND controller core.
55 tristate "Support Denali NAND controller as a DT device"
59 Enable the driver for NAND flash on platforms using a Denali NAND
[all …]
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| D | nand_ids.c | 27 * Some incompatible NAND chips share device ID's and so must be
58 LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
59 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
60 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS),
61 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xD6, 8, SZ_8K, SP_OPTIONS),
62 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xE6, 8, SZ_8K, SP_OPTIONS),
64 LEGACY_ID_NAND("NAND 16MiB 1,8V 8-bit", 0x33, 16, SZ_16K, SP_OPTIONS),
65 LEGACY_ID_NAND("NAND 16MiB 3,3V 8-bit", 0x73, 16, SZ_16K, SP_OPTIONS),
66 LEGACY_ID_NAND("NAND 16MiB 1,8V 16-bit", 0x43, 16, SZ_16K, SP_OPTIONS16),
67 LEGACY_ID_NAND("NAND 16MiB 3,3V 16-bit", 0x53, 16, SZ_16K, SP_OPTIONS16),
[all …]
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| D | jz4740_nand.c | 3 * JZ4740 SoC NAND controller driver
83 struct jz_nand *nand = mtd_to_jz_nand(mtd); in jz_nand_select_chip() local
88 ctrl = readl(nand->base + JZ_REG_NAND_CTRL); in jz_nand_select_chip()
94 banknr = nand->banks[chipnr] - 1; in jz_nand_select_chip()
95 chip->IO_ADDR_R = nand->bank_base[banknr]; in jz_nand_select_chip()
96 chip->IO_ADDR_W = nand->bank_base[banknr]; in jz_nand_select_chip()
98 writel(ctrl, nand->base + JZ_REG_NAND_CTRL); in jz_nand_select_chip()
100 nand->selected_bank = banknr; in jz_nand_select_chip()
105 struct jz_nand *nand = mtd_to_jz_nand(mtd); in jz_nand_cmd_ctrl() local
108 void __iomem *bank_base = nand->bank_base[nand->selected_bank]; in jz_nand_cmd_ctrl()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | marvell-nand.txt | 1 Marvell NAND Flash Controller (NFC)
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
16 - interrupts: shall define the NAND controller interrupt.
[all …]
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| D | nvidia-tegra20-nand.txt | 1 NVIDIA Tegra NAND Flash controller
5 - "nvidia,tegra20-nand"
11 - nand
15 - nand
18 Individual NAND chips are children of the NAND controller node. Currently
19 only one NAND chip supported.
25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
29 - nand-bus-width : See nand-controller.yaml
30 - nand-on-flash-bbt: See nand-controller.yaml
[all …]
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| D | brcm,brcmnand.txt | 1 * Broadcom STB NAND Controller
3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
19 the core NAND controller, of the following form:
35 - reg : the register start and length for NAND register region.
37 (optional) NAND flash cache range (if at non-standard offset)
39 ranges. Should contain "nand" and (optionally)
40 "flash-dma" or "flash-edu" and/or "nand-cache".
41 - interrupts : The NAND CTLRDY interrupt, (if Flash DMA is available)
45 May be "nand", if the SoC has the individual NAND
52 - clock : reference to the clock for the NAND controller
[all …]
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| D | atmel-nand.txt | 1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
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| D | denali,nand.yaml | 4 $id: http://devicetree.org/schemas/mtd/denali,nand.yaml#
7 title: Denali NAND controller
15 - altr,socfpga-denali-nand
16 - socionext,uniphier-denali-nand-v5a
17 - socionext,uniphier-denali-nand-v5b
38 nand: controller core clock
42 - const: nand
53 nand: controller core reset
57 - const: nand
59 - const: nand
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| D | qcom_nandc.txt | 1 * Qualcomm NAND controller
5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
9 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
20 NAND. Refer to dma.txt and qcom_adm.txt for more details
23 number specified for the NAND controller on the given
26 number specified for the NAND controller on the given
31 and the channel number to be used for NAND. Refer to
37 * NAND chip-select
40 chip-selects which (may) contain NAND flash chips. Their properties are as
[all …]
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| D | vf610-nfc.txt | 1 Freescale's NAND flash controller (NFC)
3 This variant of the Freescale NAND flash controller (NFC) can be found on
10 - #address-cells: shall be set to 1. Encode the nand CS.
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
14 rate and should not exceed maximum timing for any NAND memory chip
15 in a board stuffing. Typical NAND memory timings derived from this
23 Children nodes represent the available nand chips. Currently the driver can
24 only handle one NAND chip.
28 - nand-bus-width: see nand-controller.yaml
29 - nand-ecc-mode: see nand-controller.yaml
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mtd/ |
| D | marvell-nand.txt | 1 Marvell NAND Flash Controller (NFC)
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
16 - interrupts: shall define the NAND controller interrupt.
[all …]
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| D | brcm,brcmnand.txt | 1 * Broadcom STB NAND Controller
3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
19 the core NAND controller, of the following form:
32 - reg : the register start and length for NAND register region.
34 (optional) NAND flash cache range (if at non-standard offset)
36 ranges. Should contain "nand" and (optionally)
37 "flash-dma" and/or "nand-cache".
38 - interrupts : The NAND CTLRDY interrupt and (if Flash DMA is available)
42 May be "nand", if the SoC has the individual NAND
49 - clock : reference to the clock for the NAND controller
[all …]
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| D | nvidia-tegra20-nand.txt | 1 NVIDIA Tegra NAND Flash controller
5 - "nvidia,tegra20-nand"
11 - nand
15 - nand
18 Individual NAND chips are children of the NAND controller node. Currently
19 only one NAND chip supported.
25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
29 - nand-bus-width : See nand.txt
30 - nand-on-flash-bbt: See nand.txt
[all …]
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| D | nand.txt | 1 * NAND chip and NAND controller generic binding
3 NAND controller/NAND chip representation:
5 The NAND controller should be represented with its own DT node, and all
6 NAND chips attached to this controller should be defined as children nodes
7 of the NAND controller. This representation should be enforced even for
10 Mandatory NAND controller properties:
16 Optional NAND controller properties
20 Optional NAND chip properties:
22 - nand-ecc-mode : String, operation mode of the NAND ecc mode.
26 "soft_bch": use "soft" and nand-ecc-algo instead
[all …]
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| D | atmel-nand.txt | 1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
[all …]
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| D | qcom_nandc.txt | 1 * Qualcomm NAND controller
5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
9 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
20 NAND. Refer to dma.txt and qcom_adm.txt for more details
23 number specified for the NAND controller on the given
26 number specified for the NAND controller on the given
31 and the channel number to be used for NAND. Refer to
37 * NAND chip-select
40 chip-selects which (may) contain NAND flash chips. Their properties are as
[all …]
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| D | vf610-nfc.txt | 1 Freescale's NAND flash controller (NFC)
3 This variant of the Freescale NAND flash controller (NFC) can be found on
10 - #address-cells: shall be set to 1. Encode the nand CS.
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
14 rate and should not exceed maximum timing for any NAND memory chip
15 in a board stuffing. Typical NAND memory timings derived from this
23 Children nodes represent the available nand chips. Currently the driver can
24 only handle one NAND chip.
28 - nand-bus-width: see nand.txt
29 - nand-ecc-mode: see nand.txt
[all …]
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