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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
23 2) PLLs clocks generators (PLLs) - described in this binding file.
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Dbaikal,bt1-ccu-div.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
22 registers. Baikal-T1 CCU is logically divided into the next components:
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/kernel/linux/linux-5.10/drivers/thermal/ti-soc-thermal/
Dti-bandgap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
26 * +----------+----------------+
28 * +---------------------------+
32 * +-------------------+ +-----------------+
33 * | struct ti_bandgap |-->| struct device * |
34 * +----------+--------+ +-----------------+
38 * +------------------------+
40 * +------------------------+
44 * +------------+------------------------------------------------------+
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/kernel/linux/linux-4.19/drivers/thermal/ti-soc-thermal/
Dti-bandgap.h4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
20 * 02110-1301 USA
34 * +----------+----------------+
36 * +---------------------------+
40 * +-------------------+ +-----------------+
41 * | struct ti_bandgap |-->| struct device * |
42 * +----------+--------+ +-----------------+
46 * +------------------------+
48 * +------------------------+
52 * +------------+------------------------------------------------------+
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/kernel/linux/linux-4.19/drivers/mtd/nand/raw/brcmnand/
Dbrcmnand.c2 * Copyright © 2010-2015 Broadcom Corporation
25 #include <linux/dma-mapping.h>
128 /* Some SoCs have a gateable clock for the controller */
136 /* List of NAND hosts (one for each chip-select) */
142 /* in-memory cache of the FLASH_CACHE, used only for some commands */
148 const u8 *cs_offsets; /* within each chip-select */
157 /* for low-power standby/resume only */
175 /* use for low-power standby/resume only */
206 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
220 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
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/kernel/linux/linux-5.10/drivers/mtd/nand/raw/brcmnand/
Dbrcmnand.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2010-2015 Broadcom Corporation
16 #include <linux/dma-mapping.h>
223 /* Some SoCs have a gateable clock for the controller */
233 /* List of NAND hosts (one for each chip-select) */
236 /* EDU info, per-transaction */
254 /* in-memory cache of the FLASH_CACHE, used only for some commands */
260 const u8 *cs_offsets; /* within each chip-select */
270 /* for low-power standby/resume only */
290 /* use for low-power standby/resume only */
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