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Searched +full:phy +full:- +full:pma (Results 1 – 25 of 51) sorted by relevance

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/kernel/linux/linux-4.19/include/uapi/linux/
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
22 #define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
40 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
41 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
42 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
49 #define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
53 /* Media-dependent registers. */
54 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
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/kernel/linux/linux-5.10/include/uapi/linux/
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
22 #define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
40 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
41 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
42 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
49 #define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */
51 #define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
57 /* Media-dependent registers. */
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/kernel/linux/linux-5.10/drivers/net/phy/
Dphy-c45.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Clause 45 PHY support
9 #include <linux/phy.h>
12 * genphy_c45_setup_forced - configures a forced speed
20 if (phydev->duplex != DUPLEX_FULL) in genphy_c45_pma_setup_forced()
21 return -EINVAL; in genphy_c45_pma_setup_forced()
33 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1 in genphy_c45_pma_setup_forced()
34 * in 802.3-2012 and 802.3-2015. in genphy_c45_pma_setup_forced()
38 switch (phydev->speed) { in genphy_c45_pma_setup_forced()
48 /* Assume 1000base-T */ in genphy_c45_pma_setup_forced()
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Dmarvell10g.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell 10G 88x3310 PHY driver
5 * Based upon the ID registers, this PHY appears to be a mixture of IPs
8 * There appears to be several different data paths through the PHY which
9 * are automatically managed by the PHY. The following has been determined
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
18 * XAUI PHYXS -- <appropriate PCS as above>
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Daquantia_main.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Aquantia PHY
14 #include <linux/phy.h>
166 int len_l = min(stat->size, 16); in aqr107_get_stat()
167 int len_h = stat->size - len_l; in aqr107_get_stat()
171 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); in aqr107_get_stat()
175 ret = val & GENMASK(len_l - 1, 0); in aqr107_get_stat()
177 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); in aqr107_get_stat()
181 ret += (val & GENMASK(len_h - 1, 0)) << 16; in aqr107_get_stat()
190 struct aqr107_priv *priv = phydev->priv; in aqr107_get_stats()
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dsamsung,ufs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC series UFS PHY Device Tree Bindings
10 - Alim Akhtar <alim.akhtar@samsung.com>
13 "#phy-cells":
18 - samsung,exynos7-ufs-phy
23 reg-names:
25 - const: phy-pma
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Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
19 power-domains:
24 description: clock-specifier to represent input to the WIZ
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/kernel/linux/linux-4.19/drivers/net/phy/
Dphy-c45.c2 * Clause 45 PHY support
8 #include <linux/phy.h>
11 * genphy_c45_setup_forced - configures a forced speed
19 if (phydev->duplex != DUPLEX_FULL) in genphy_c45_pma_setup_forced()
20 return -EINVAL; in genphy_c45_pma_setup_forced()
32 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1 in genphy_c45_pma_setup_forced()
33 * in 802.3-2012 and 802.3-2015. in genphy_c45_pma_setup_forced()
37 switch (phydev->speed) { in genphy_c45_pma_setup_forced()
47 /* Assume 1000base-T */ in genphy_c45_pma_setup_forced()
52 /* Assume 10Gbase-T */ in genphy_c45_pma_setup_forced()
[all …]
Dmarvell10g.c2 * Marvell 10G 88x3310 PHY driver
4 * Based upon the ID registers, this PHY appears to be a mixture of IPs
7 * There appears to be several different data paths through the PHY which
8 * are automatically managed by the PHY. The following has been determined
9 * via observation and experimentation for a setup using single-lane Serdes:
11 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
12 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
13 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
17 * XAUI PHYXS -- <appropriate PCS as above>
27 #include <linux/phy.h>
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/kernel/linux/linux-5.10/drivers/net/ethernet/sfc/falcon/
Dqt202x_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2012 Solarflare Communications Inc.
15 #include "phy.h"
27 /* Quake-specific MDIO registers */
85 ((1 << PCS_FW_HEARTB_WIDTH) - 1)); in qt2025c_wait_heartbeat()
92 * PHY's on-board EEPROM so it cannot load firmware */ in qt2025c_wait_heartbeat()
93 netif_err(efx, hw, efx->net_dev, in qt2025c_wait_heartbeat()
97 return -ETIMEDOUT; in qt2025c_wait_heartbeat()
116 ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >= in qt2025c_wait_fw_status_good()
120 return -ETIMEDOUT; in qt2025c_wait_fw_status_good()
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Dtxc43128_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2011 Solarflare Communications Inc.
9 * see www.transwitch.com, part is TXC-43128
16 #include "phy.h"
30 * Compile-time config
35 /* Total length of time we'll wait for the PHY to come out of reset (ms) */
52 /* Lane power-down */
56 * initiates a logic reset. Self-clearing */
69 /* Lane power-down */
108 /* Lane power-down */
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/kernel/linux/linux-4.19/drivers/net/ethernet/sfc/falcon/
Dqt202x_phy.c3 * Copyright 2006-2012 Solarflare Communications Inc.
18 #include "phy.h"
30 /* Quake-specific MDIO registers */
88 ((1 << PCS_FW_HEARTB_WIDTH) - 1)); in qt2025c_wait_heartbeat()
95 * PHY's on-board EEPROM so it cannot load firmware */ in qt2025c_wait_heartbeat()
96 netif_err(efx, hw, efx->net_dev, in qt2025c_wait_heartbeat()
100 return -ETIMEDOUT; in qt2025c_wait_heartbeat()
119 ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >= in qt2025c_wait_fw_status_good()
123 return -ETIMEDOUT; in qt2025c_wait_fw_status_good()
147 if (rc == -ETIMEDOUT) { in qt2025c_wait_reset()
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Dtxc43128_phy.c3 * Copyright 2006-2011 Solarflare Communications Inc.
12 * see www.transwitch.com, part is TXC-43128
19 #include "phy.h"
33 * Compile-time config
38 /* Total length of time we'll wait for the PHY to come out of reset (ms) */
55 /* Lane power-down */
59 * initiates a logic reset. Self-clearing */
72 /* Lane power-down */
111 /* Lane power-down */
128 /* Vendor-specific BIST registers */
[all …]
/kernel/linux/linux-5.10/drivers/phy/cadence/
Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence Torrent SD0801 PHY driver.
9 #include <dt-bindings/phy/phy.h>
20 #include <linux/phy/phy.h>
56 * register offsets from DPTX PHY register block base (i.e MHDP
76 * register offsets from SD0801 PHY register block base (i.e MHDP
161 /* PMA TX Lane registers */
180 /* PMA RX Lane registers */
208 /* PHY PCS common registers */
214 /* PHY PMA common registers */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/
Dcdns,mhdp8546.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
16 - cdns,mhdp8546
17 - ti,j721e-mhdp8546
23 - description:
24 Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
25 The AUX and PMA registers are not part of this range, they are instead
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/kernel/linux/linux-5.10/drivers/phy/samsung/
Dphy-samsung-ufs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * UFS PHY driver for Samsung SoC
18 #include <linux/phy/phy.h>
22 #include "phy-samsung-ufs.h"
24 #define for_each_phy_lane(phy, i) \ argument
25 for (i = 0; i < (phy)->lane_cnt; i++)
27 for (; (cfg)->id; (cfg)++)
31 static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy, in samsung_ufs_phy_config() argument
39 writel(cfg->val, (phy)->reg_pma + cfg->off_0); in samsung_ufs_phy_config()
42 if (cfg->id == PHY_TRSV_BLK) in samsung_ufs_phy_config()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/xilinx/
Dxilinx_axienet.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
147 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
157 #define XAE_PPST_OFFSET 0x00000030 /* PCS PMA Soft Temac Status Reg */
200 /* Transmit inter-frame gap adjustment value */
216 #define XAE_INT_PHYRSTCMPLT_MASK 0x00000100 /* Phy Reset complete */
234 /* In-Band FCS enable (FCS not stripped) */
250 /* In-Band FCS enable (FCS not generated) */
254 /* Inter-frame gap adjustment enable */
276 #define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/exynos/
Dexynos7.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos7-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
31 arm-pmu {
32 compatible = "arm,cortex-a57-pmu";
37 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
43 compatible = "fixed-clock";
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/kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb3/
Dael1002.c2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
62 /* PHY module I2C device address */
68 /* PHY transceiver type */
84 static int set_phy_regs(struct cphy *phy, const struct reg_val *rv) in set_phy_regs() argument
88 for (err = 0; rv->mmd_addr && !err; rv++) { in set_phy_regs()
89 if (rv->clear_bits == 0xffff) in set_phy_regs()
90 err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr, in set_phy_regs()
91 rv->set_bits); in set_phy_regs()
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/chelsio/cxgb3/
Dael1002.c2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
62 /* PHY module I2C device address */
68 /* PHY transceiver type */
84 static int set_phy_regs(struct cphy *phy, const struct reg_val *rv) in set_phy_regs() argument
88 for (err = 0; rv->mmd_addr && !err; rv++) { in set_phy_regs()
89 if (rv->clear_bits == 0xffff) in set_phy_regs()
90 err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr, in set_phy_regs()
91 rv->set_bits); in set_phy_regs()
[all …]
/kernel/linux/linux-5.10/drivers/phy/ti/
Dphy-am654-serdes.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
11 #include <linux/clk-provider.h>
17 #include <linux/phy/phy.h>
119 /* AHB PMA Lane Configuration */
142 /* Mid-speed initial calibration control */
145 /* High-speed initial calibration control */
148 /* Mid-speed recalibration control */
151 /* High-speed recalibration control */
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/kernel/linux/linux-5.10/drivers/phy/xilinx/
Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
22 #include <linux/phy/phy.h>
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
41 /* PMA control parameters */
170 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
184 * struct xpsgtr_phy - representation of a lane
185 * @phy: pointer to the kernel PHY device
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/kernel/linux/linux-5.10/drivers/net/
Dmdio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * mdio.c: Generic support for MDIO-compatible transceivers
4 * Copyright 2006-2009 Solarflare Communications Inc.
14 MODULE_DESCRIPTION("Generic support for MDIO-compatible transceivers");
15 MODULE_AUTHOR("Copyright 2006-2009 Solarflare Communications Inc.");
19 * mdio45_probe - probe for an MDIO (clause 45) device
21 * @prtad: Expected PHY address
30 /* Assume PHY must have at least one of PMA/PMD, WIS, PCS, PHY in mdio45_probe()
34 stat2 = mdio->mdio_read(mdio->dev, prtad, mmd, MDIO_STAT2); in mdio45_probe()
40 devs1 = mdio->mdio_read(mdio->dev, prtad, mmd, MDIO_DEVS1); in mdio45_probe()
[all …]
/kernel/linux/linux-4.19/drivers/net/
Dmdio.c2 * mdio.c: Generic support for MDIO-compatible transceivers
3 * Copyright 2006-2009 Solarflare Communications Inc.
17 MODULE_DESCRIPTION("Generic support for MDIO-compatible transceivers");
18 MODULE_AUTHOR("Copyright 2006-2009 Solarflare Communications Inc.");
22 * mdio45_probe - probe for an MDIO (clause 45) device
24 * @prtad: Expected PHY address
33 /* Assume PHY must have at least one of PMA/PMD, WIS, PCS, PHY in mdio45_probe()
37 stat2 = mdio->mdio_read(mdio->dev, prtad, mmd, MDIO_STAT2); in mdio45_probe()
43 devs1 = mdio->mdio_read(mdio->dev, prtad, mmd, MDIO_DEVS1); in mdio45_probe()
44 devs2 = mdio->mdio_read(mdio->dev, prtad, mmd, MDIO_DEVS2); in mdio45_probe()
[all …]
/kernel/linux/linux-5.10/drivers/scsi/bfa/
Dbfa_defs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
4 * Copyright (c) 2014- QLogic Corporation.
8 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
34 BFA_MFG_TYPE_LIGHTNING_P0 = 902, /* Lightning mezz card - old */
102 * All numerical fields are in big-endian format.
125 BFA_STATUS_ETIMER = 5, /* Timer expired - Retry, if persists,
129 BFA_STATUS_SFP_UNSUPP = 10, /* Unsupported SFP - Replace SFP */
132 BFA_STATUS_DEVBUSY = 13, /* Device busy - Retry operation */
148 BFA_STATUS_IOC_FAILURE = 56, /* IOC failure - Retry, if persists
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