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Searched +full:phy +full:- +full:qcom +full:- +full:qusb2 (Results 1 – 15 of 15) sorted by relevance

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dqcom,qusb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QUSB2 phy controller
11 - Manu Gautam <mgautam@codeaurora.org>
14 QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
19 - items:
20 - enum:
21 - qcom,ipq8074-qusb2-phy
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/phy/
Dqcom-qusb2-phy.txt1 Qualcomm QUSB2 phy controller
4 QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
7 - compatible: compatible list, contains
8 "qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996,
9 "qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845.
11 - reg: offset and length of the PHY register set.
12 - #phy-cells: must be 0.
14 - clocks: a list of phandles and clock-specifier pairs,
15 one for each entry in clock-names.
16 - clock-names: must be "cfg_ahb" for phy config clock,
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/usb/
Dqcom,dwc3.txt4 - compatible: Compatible list, contains
5 "qcom,dwc3"
6 "qcom,msm8996-dwc3" for msm8996 SOC.
7 "qcom,sdm845-dwc3" for sdm845 SOC.
8 - reg: Offset and length of register set for QSCRATCH wrapper
9 - power-domains: specifies a phandle to PM domain provider node
10 - clocks: A list of phandle + clock-specifier pairs for the
11 clocks listed in clock-names
12 - clock-names: Should contain the following:
22 Not present on "qcom,msm8996-dwc3" compatible.
[all …]
/kernel/linux/linux-5.10/drivers/phy/qualcomm/
Dphy-qcom-qusb2.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/nvmem-consumer.h>
16 #include <linux/phy/phy.h>
23 #include <dt-bindings/phy/phy-qcom-qusb2.h>
105 * if yes, then offset gives index in the reg-layout
123 /* set of registers with offsets different per-PHY */
240 /* true if PHY has PLL_TEST register to select clk_scheme */
246 /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
287 "vdda-pll", "vdda-phy-dpdm",
292 /* struct override_param - structure holding qusb2 v2 phy overriding param
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o
3 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
4 obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
5 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
6 obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
7 obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
8 obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
9 obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
10 obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Qualcomm and Atheros platforms
6 tristate "Atheros AR71XX/9XXX USB PHY driver"
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
15 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
22 tristate "Qualcomm IPQ4019 USB PHY driver"
26 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
29 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
36 tristate "Qualcomm PCIe Gen2 PHY Driver"
40 Enable this to support the Qualcomm PCIe PHY, used with the Synopsys
[all …]
/kernel/linux/linux-4.19/drivers/phy/qualcomm/
DKconfig2 # Phy drivers for Qualcomm and Atheros platforms
5 tristate "Atheros AR71XX/9XXX USB PHY driver"
11 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
14 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
21 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
28 tristate "Qualcomm QMP PHY Driver"
32 Enable this to support the QMP PHY transceiver that is used
36 tristate "Qualcomm QUSB2 PHY Driver"
41 Enable this to support the HighSpeed QUSB2 PHY transceiver for USB
42 controllers on Qualcomm chips. This driver supports the high-speed
[all …]
Dphy-qcom-qusb2.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/nvmem-consumer.h>
16 #include <linux/phy/phy.h>
23 #include <dt-bindings/phy/phy-qcom-qusb2.h>
93 * if yes, then offset gives index in the reg-layout
111 /* set of registers with offsets different per-PHY */
203 /* true if PHY has PLL_TEST register to select clk_scheme */
209 /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
238 "vdda-pll", "vdda-phy-dpdm",
244 * struct qusb2_phy - structure holding qusb2 phy attributes
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o
3 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
4 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
5 obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
6 obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
7 obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs.o
8 obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-14nm.o
9 obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-20nm.o
10 obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/
Dipq8074.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
11 compatible = "qcom,ipq8074";
15 compatible = "fixed-clock";
16 clock-frequency = <32000>;
17 #clock-cells = <0>;
21 compatible = "fixed-clock";
22 clock-frequency = <19200000>;
23 #clock-cells = <0>;
[all …]
Dsdm845.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sdm845.h>
[all …]
Dmsm8996.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,apr.h>
12 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
[all …]
Dsc7180.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sc7180.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
[all …]
Dmsm8998.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/gpio/gpio.h>
12 interrupt-parent = <&intc>;
14 qcom,msm-id = <292 0x0>;
16 #address-cells = <2>;
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/qcom/
Dmsm8996.dtsi1 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
15 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
16 #include <dt-bindings/clock/qcom,rpmcc.h>
21 interrupt-parent = <&intc>;
23 #address-cells = <2>;
24 #size-cells = <2>;
34 reserved-memory {
35 #address-cells = <2>;
[all …]