| /kernel/linux/linux-4.19/drivers/clk/mediatek/ |
| D | clk-pll.c | 22 #include "clk-mtk.h"
29 #define CON0_ISO_EN BIT(1)
39 * a divider in the PLL feedback loop which consists of 7 bits for the integer
41 * have a 3 bit power-of-two post divider.
62 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_is_prepared() local
64 return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; in mtk_pll_is_prepared()
67 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, in __mtk_pll_recalc_rate() argument
70 int pcwbits = pll->data->pcwbits; in __mtk_pll_recalc_rate()
75 /* The fractional part of the PLL divider. */ in __mtk_pll_recalc_rate()
76 pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0; in __mtk_pll_recalc_rate()
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| /kernel/linux/linux-5.10/drivers/clk/mediatek/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 #include "clk-mtk.h"
21 #define CON0_ISO_EN BIT(1)
33 * a divider in the PLL feedback loop which consists of 7 bits for the integer
35 * have a 3 bit power-of-two post divider.
57 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_is_prepared() local
59 return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; in mtk_pll_is_prepared()
62 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, in __mtk_pll_recalc_rate() argument
65 int pcwbits = pll->data->pcwbits; in __mtk_pll_recalc_rate()
71 /* The fractional part of the PLL divider. */ in __mtk_pll_recalc_rate()
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| /kernel/linux/linux-5.10/drivers/clk/tegra/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
159 #define PLLSS_EN_DITHER 1
196 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
207 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
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| /kernel/linux/linux-4.19/drivers/clk/tegra/ |
| D | clk-pll.c | 22 #include <linux/clk-provider.h>
42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
170 #define PLLSS_EN_DITHER 1
207 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
218 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
241 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
242 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
243 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
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| /kernel/linux/linux-4.19/drivers/clk/qcom/ |
| D | clk-alpha-pll.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
12 #include "clk-alpha-pll.h"
15 #define PLL_MODE(p) ((p)->offset + 0x0)
17 # define PLL_BYPASSNL BIT(1)
34 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
35 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
36 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
38 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
40 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
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| D | clk-pll.c | 20 #include <linux/clk-provider.h>
25 #include "clk-pll.h"
29 #define PLL_BYPASSNL BIT(1)
34 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
39 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
47 /* Disable PLL bypass mode. */ in clk_pll_enable()
48 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
55 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
59 /* De-assert active-low PLL reset. */ in clk_pll_enable()
60 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
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| /kernel/linux/linux-4.19/drivers/video/fbdev/aty/ |
| D | mach64_ct.c | 1 // SPDX-License-Identifier: GPL-2.0
18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
53 * CLK = ----------------------
64 * are 1,2,4,8 and for some clocks other values are available too.
70 * XCLK The clock rate of the on-chip memory
77 * SCLK Multi-purpose clock
79 * - MCLK and XCLK use the same FB_DIV
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| /kernel/linux/linux-5.10/drivers/video/fbdev/aty/ |
| D | mach64_ct.c | 1 // SPDX-License-Identifier: GPL-2.0
18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
53 * CLK = ----------------------
64 * are 1,2,4,8 and for some clocks other values are available too.
70 * XCLK The clock rate of the on-chip memory
77 * SCLK Multi-purpose clock
79 * - MCLK and XCLK use the same FB_DIV
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/baikal-t1/ |
| D | ccu-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU PLL interface driver
12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt
20 #include <linux/clk-provider.h>
29 #include "ccu-pll.h"
33 #define CCU_PLL_CTL_RST BIT(1)
49 ((CCU_PLL_CTL_CLKR_MASK >> CCU_PLL_CTL_CLKR_FLD) + 1)
51 ((CCU_PLL_CTL_CLKF_MASK >> (CCU_PLL_CTL_CLKF_FLD + 1)) + 1)
53 ((CCU_PLL_CTL_CLKOD_MASK >> CCU_PLL_CTL_CLKOD_FLD) + 1)
55 ((CCU_PLL_CTL1_BWADJ_MASK >> CCU_PLL_CTL1_BWADJ_FLD) + 1)
[all …]
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| /kernel/linux/linux-4.19/drivers/clk/sprd/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Spreadtrum pll clock driver
13 #include "pll.h"
18 #define pindex(pll, member) \ argument
19 (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
21 #define pshift(pll, member) \ argument
22 (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
24 #define pwidth(pll, member) \ argument
25 pll->factors[member].width
27 #define pmask(pll, member) \ argument
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| /kernel/linux/linux-5.10/arch/mips/ath79/ |
| D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
17 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/ath79-clk.h>
24 #include <asm/mach-ath79/ath79.h>
25 #include <asm/mach-ath79/ar71xx_regs.h>
99 u32 pll; in ar71xx_clocks_init() local
105 pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init()
107 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1; in ar71xx_clocks_init()
110 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; in ar71xx_clocks_init()
[all …]
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| /kernel/linux/linux-5.10/drivers/media/i2c/ |
| D | smiapp-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/media/i2c/smiapp-pll.c
7 * Copyright (C) 2011--2012 Nokia Corporation
16 #include "smiapp-pll.h"
21 return max_t(uint32_t, 1, a & ~1); in clk_div_even()
27 if (a == 1) in clk_div_even_up()
28 return 1; in clk_div_even_up()
29 return (a + 1) & ~1; in clk_div_even_up()
34 if (a == 1) in is_one_or_even()
35 return 1; in is_one_or_even()
[all …]
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| /kernel/linux/linux-4.19/drivers/media/i2c/ |
| D | smiapp-pll.c | 2 * drivers/media/i2c/smiapp-pll.c
6 * Copyright (C) 2011--2012 Nokia Corporation
24 #include "smiapp-pll.h"
29 return max_t(uint32_t, 1, a & ~1); in clk_div_even()
35 if (a == 1) in clk_div_even_up()
36 return 1; in clk_div_even_up()
37 return (a + 1) & ~1; in clk_div_even_up()
42 if (a == 1) in is_one_or_even()
43 return 1; in is_one_or_even()
44 if (a & 1) in is_one_or_even()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/rockchip/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
56 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
67 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_pll_round_rate() local
68 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_pll_round_rate()
72 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_round_rate()
78 return rate_table[i - 1].rate; in rockchip_pll_round_rate()
[all …]
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| /kernel/linux/linux-4.19/drivers/clk/rockchip/ |
| D | clk-pll.c | 6 * Author: Xing Zheng <zhengxing@rock-chips.com>
23 #include <linux/clk-provider.h>
59 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
61 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
64 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
75 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_pll_round_rate() local
76 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_pll_round_rate()
80 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_round_rate()
86 return rate_table[i - 1].rate; in rockchip_pll_round_rate()
90 * Wait for the pll to reach the locked state.
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| D | clk-alpha-pll.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
12 #include "clk-alpha-pll.h"
15 #define PLL_MODE(p) ((p)->offset + 0x0)
17 # define PLL_BYPASSNL BIT(1)
34 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
35 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
36 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
37 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
39 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
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| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
21 #define PLL_BYPASSNL BIT(1)
26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
51 /* De-assert active-low PLL reset. */ in clk_pll_enable()
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| /kernel/linux/linux-5.10/drivers/clk/meson/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * In the most basic form, a Meson PLL is composed as follows:
13 * PLL
14 * +--------------------------------+
16 * | +--+ |
17 * in >>-----[ /N ]--->| | +-----+ |
18 * | | |------| DCO |---->> out
19 * | +--------->| | +--v--+ |
20 * | | +--+ | |
22 * | +--[ *(M + (F/Fmax) ]<--+ |
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| /kernel/linux/linux-5.10/drivers/clk/sprd/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Spreadtrum pll clock driver
13 #include "pll.h"
18 #define pindex(pll, member) \ argument
19 (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
21 #define pshift(pll, member) \ argument
22 (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
24 #define pwidth(pll, member) \ argument
25 pll->factors[member].width
27 #define pmask(pll, member) \ argument
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| /kernel/linux/linux-4.19/drivers/clk/bcm/ |
| D | clk-iproc-pll.c | 16 #include <linux/clk-provider.h>
23 #include "clk-iproc.h"
29 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
30 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
34 /* number of delay loops waiting for PLL to lock */
85 struct iproc_pll *pll; member
100 return -EINVAL; in pll_calc_param()
102 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param()
112 vco_out->ndiv_int = ndiv_int; in pll_calc_param()
113 vco_out->ndiv_frac = ndiv_frac; in pll_calc_param()
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| /kernel/linux/linux-5.10/drivers/clk/bcm/ |
| D | clk-iproc-pll.c | 16 #include <linux/clk-provider.h>
23 #include "clk-iproc.h"
29 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
30 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
34 /* number of delay loops waiting for PLL to lock */
85 struct iproc_pll *pll; member
100 return -EINVAL; in pll_calc_param()
102 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param()
112 vco_out->ndiv_int = ndiv_int; in pll_calc_param()
113 vco_out->ndiv_frac = ndiv_frac; in pll_calc_param()
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| /kernel/linux/linux-4.19/arch/mips/ath79/ |
| D | clock.c | 4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
19 #include <linux/clk-provider.h>
22 #include <dt-bindings/clock/ath79-clk.h>
26 #include <asm/mach-ath79/ath79.h>
27 #include <asm/mach-ath79/ar71xx_regs.h>
63 u32 pll; in ar71xx_clocks_init() local
69 pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init()
71 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1; in ar71xx_clocks_init()
74 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; in ar71xx_clocks_init()
77 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; in ar71xx_clocks_init()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/pll/ |
| D | dsi_pll_14nm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 * DSI PLL 14nm - clock diagram (eg: DSI0):
18 * +----+ | +----+
19 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
20 * +----+ | +----+
22 * | +----+ |
23 * o---| /2 |--o--|\
24 * | +----+ | \ +----+
25 * | | |--| n2 |-- dsi0pll
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| /kernel/linux/linux-4.19/drivers/gpu/drm/msm/dsi/pll/ |
| D | dsi_pll_14nm.c | 15 #include <linux/clk-provider.h>
21 * DSI PLL 14nm - clock diagram (eg: DSI0):
26 * +----+ | +----+
27 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
28 * +----+ | +----+
30 * | +----+ |
31 * o---| /2 |--o--|\
32 * | +----+ | \ +----+
33 * | | |--| n2 |-- dsi0pll
34 * o--------------| / +----+
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| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-pll14xx.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2017-2018 NXP.
7 #include <linux/clk-provider.h>
48 PLL_1416X_RATE(1500000000U, 375, 3, 1),
49 PLL_1416X_RATE(1400000000U, 350, 3, 1),
50 PLL_1416X_RATE(1200000000U, 300, 3, 1),
51 PLL_1416X_RATE(1000000000U, 250, 3, 1),
52 PLL_1416X_RATE(800000000U, 200, 3, 1),
59 PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
90 struct clk_pll14xx *pll, unsigned long rate) in imx_get_pll_settings() argument
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