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/kernel/linux/linux-4.19/drivers/clk/sunxi/
Dclk-a10-pll2.c24 #include <dt-bindings/clock/sun4i-a10-pll2.h>
70 prediv_clk = clk_register_divider(NULL, "pll2-prediv", in sun4i_pll2_setup()
81 /* Setup the gate part of the PLL2 */ in sun4i_pll2_setup()
90 /* Setup the multiplier part of the PLL2 */ in sun4i_pll2_setup()
103 base_clk = clk_register_composite(NULL, "pll2-base", in sun4i_pll2_setup()
117 * PLL2-1x in sun4i_pll2_setup()
138 * PLL2-2x in sun4i_pll2_setup()
141 * a fixed divider from the PLL2 base clock. in sun4i_pll2_setup()
151 /* PLL2-4x */ in sun4i_pll2_setup()
160 /* PLL2-8x */ in sun4i_pll2_setup()
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/kernel/linux/linux-5.10/drivers/clk/sunxi/
Dclk-a10-pll2.c16 #include <dt-bindings/clock/sun4i-a10-pll2.h>
62 prediv_clk = clk_register_divider(NULL, "pll2-prediv", in sun4i_pll2_setup()
73 /* Setup the gate part of the PLL2 */ in sun4i_pll2_setup()
82 /* Setup the multiplier part of the PLL2 */ in sun4i_pll2_setup()
95 base_clk = clk_register_composite(NULL, "pll2-base", in sun4i_pll2_setup()
109 * PLL2-1x in sun4i_pll2_setup()
130 * PLL2-2x in sun4i_pll2_setup()
133 * a fixed divider from the PLL2 base clock. in sun4i_pll2_setup()
143 /* PLL2-4x */ in sun4i_pll2_setup()
152 /* PLL2-8x */ in sun4i_pll2_setup()
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/kernel/linux/linux-5.10/include/linux/iio/frequency/
Dad9523.h126 * @pll2_charge_pump_current_nA: Magnitude of PLL2 charge pump current (nA).
127 * @pll2_ndiv_a_cnt: PLL2 Feedback N-divider, A Counter, range 0..4.
128 * @pll2_ndiv_b_cnt: PLL2 Feedback N-divider, B Counter, range 0..63.
129 * @pll2_freq_doubler_en: PLL2 frequency doubler enable.
130 * @pll2_r2_div: PLL2 R2 divider, range 0..31.
133 * @rpole2: PLL2 loop filter Rpole resistor value.
134 * @rzero: PLL2 loop filter Rzero resistor value.
135 * @cpole1: PLL2 loop filter Cpole capacitor value.
136 * @rzero_bypass_en: PLL2 loop filter Rzero bypass enable.
172 /* PLL2 Setting */
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/kernel/linux/linux-4.19/include/linux/iio/frequency/
Dad9523.h127 * @pll2_charge_pump_current_nA: Magnitude of PLL2 charge pump current (nA).
128 * @pll2_ndiv_a_cnt: PLL2 Feedback N-divider, A Counter, range 0..4.
129 * @pll2_ndiv_b_cnt: PLL2 Feedback N-divider, B Counter, range 0..63.
130 * @pll2_freq_doubler_en: PLL2 frequency doubler enable.
131 * @pll2_r2_div: PLL2 R2 divider, range 0..31.
134 * @rpole2: PLL2 loop filter Rpole resistor value.
135 * @rzero: PLL2 loop filter Rzero resistor value.
136 * @cpole1: PLL2 loop filter Cpole capacitor value.
137 * @rzero_bypass_en: PLL2 loop filter Rzero bypass enable.
173 /* PLL2 Setting */
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dallwinner,sun4i-a10-mod1-clk.yaml44 #include <dt-bindings/clock/sun4i-a10-pll2.h>
50 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
51 <&pll2 SUN4I_A10_PLL2_4X>,
52 <&pll2 SUN4I_A10_PLL2_2X>,
53 <&pll2 SUN4I_A10_PLL2_1X>;
Dti,cdce925.txt30 For all PLL1, PLL2, ... an optional child node can be used to specify spread
49 PLL2 {
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/fsl/
Dp4080si-post.dtsi378 pll2: pll2@840 { label
383 clock-output-names = "pll2", "pll2-div2";
416 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
417 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
425 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
426 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
434 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
435 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
443 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
444 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
Dt4240si-post.dtsi954 pll2: pll2@840 { label
959 clock-output-names = "pll2", "pll2-div2", "pll2-div4";
984 <&pll2 0>, <&pll2 1>, <&pll2 2>;
987 "pll2", "pll2-div2", "pll2-div4";
997 <&pll2 0>, <&pll2 1>, <&pll2 2>;
1000 "pll2", "pll2-div2", "pll2-div4";
/kernel/liteos_m/targets/riscv_nuclei_gd32vf103_soc_gcc/SoC/gd32vf103/Common/Include/
Dgd32vf103_rcu.h74 #define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */
75 #define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization fla…
99 #define RCU_INT_PLL2STBIF BIT(6) /*!< PLL2 stabilization interrupt…
107 #define RCU_INT_PLL2STBIE BIT(14) /*!< PLL2 stabilization interrupt…
114 #define RCU_INT_PLL2STBIC BIT(22) /*!< PLL2 stabilization interrupt…
223 #define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication fa…
397 RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */
417 …RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt fl…
429 …RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrup…
441 RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */
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/kernel/linux/linux-5.10/sound/soc/codecs/
Dak4642.c114 #define PLL2 (1 << 6) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
345 pll = PLL2; in ak4642_dai_set_sysclk()
348 pll = PLL2 | PLL0; in ak4642_dai_set_sysclk()
351 pll = PLL2 | PLL1; in ak4642_dai_set_sysclk()
354 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
357 pll = PLL3 | PLL2; in ak4642_dai_set_sysclk()
360 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
367 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
/kernel/linux/linux-4.19/sound/soc/codecs/
Dak4642.c114 #define PLL2 (1 << 6) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
345 pll = PLL2; in ak4642_dai_set_sysclk()
348 pll = PLL2 | PLL0; in ak4642_dai_set_sysclk()
351 pll = PLL2 | PLL1; in ak4642_dai_set_sysclk()
354 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
357 pll = PLL3 | PLL2; in ak4642_dai_set_sysclk()
360 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
367 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
/kernel/linux/linux-5.10/drivers/mfd/
Dsm501.c116 static unsigned long decode_div(unsigned long pll2, unsigned long val, in decode_div() argument
121 pll2 = 288 * MHZ; in decode_div()
123 return pll2 / div_tab[(val >> lshft) & mask]; in decode_div()
140 unsigned long pll2 = 0; in sm501_dump_clk() local
144 pll2 = 336 * MHZ; in sm501_dump_clk()
147 pll2 = 288 * MHZ; in sm501_dump_clk()
150 pll2 = 240 * MHZ; in sm501_dump_clk()
153 pll2 = 192 * MHZ; in sm501_dump_clk()
157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/
Drenesas,r8a73a4-cpg-clocks.txt17 "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
29 clock-output-names = "main", "pll0", "pll1", "pll2",
Drenesas,sh73a0-cpg-clocks.txt19 "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
31 clock-output-names = "main", "pll0", "pll1", "pll2",
Dti,cdce925.txt28 For all PLL1, PLL2, ... an optional child node can be used to specify spread
45 PLL2 {
/kernel/linux/linux-4.19/drivers/mfd/
Dsm501.c118 static unsigned long decode_div(unsigned long pll2, unsigned long val, in decode_div() argument
123 pll2 = 288 * MHZ; in decode_div()
125 return pll2 / div_tab[(val >> lshft) & mask]; in decode_div()
142 unsigned long pll2 = 0; in sm501_dump_clk() local
146 pll2 = 336 * MHZ; in sm501_dump_clk()
149 pll2 = 288 * MHZ; in sm501_dump_clk()
152 pll2 = 240 * MHZ; in sm501_dump_clk()
155 pll2 = 192 * MHZ; in sm501_dump_clk()
159 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
162 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/dispnv04/
Dhw.c133 uint32_t pll2, struct nvkm_pll_vals *pllvals) in nouveau_hw_decode_pll() argument
137 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */ in nouveau_hw_decode_pll()
144 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
147 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) in nouveau_hw_decode_pll()
151 pllvals->NM2 = pll2 & 0xffff; in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
180 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
184 pll2 = nvif_rd32(device, reg2); in nouveau_hw_get_pllvals()
193 pll2 = 0; in nouveau_hw_get_pllvals()
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/kernel/linux/linux-4.19/drivers/gpu/drm/nouveau/dispnv04/
Dhw.c133 uint32_t pll2, struct nvkm_pll_vals *pllvals) in nouveau_hw_decode_pll() argument
137 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */ in nouveau_hw_decode_pll()
144 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
147 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) in nouveau_hw_decode_pll()
151 pllvals->NM2 = pll2 & 0xffff; in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
180 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
184 pll2 = nvif_rd32(device, reg2); in nouveau_hw_get_pllvals()
193 pll2 = 0; in nouveau_hw_get_pllvals()
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/kernel/linux/linux-5.10/drivers/clk/mmp/
Dclk-of-mmp2.c108 {MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10},
113 …{MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10, 26000000…
128 {MMP2_CLK_PLL2_2, "pll2_2", "pll2", 1, 2, 0},
132 {MMP2_CLK_PLL2_3, "pll2_3", "pll2", 1, 3, 0},
301 static const char * const sdh_parent_names[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
312 static const char * const disp_parent_names[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
319 … * const mmp2_gpu_gc_parent_names[] = {"pll1_2", "pll1_3", "pll2_2", "pll2_3", "pll2", "usb_pll"};
321 static const char * const mmp2_gpu_bus_parent_names[] = {"pll1_4", "pll2", "pll2_2", "usb_pll"};
324 static const char * const mmp3_gpu_gc_parent_names[] = {"pll1", "pll2", "pll1_p", "pll2_p"};
Dclk-mmp2.c72 static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
73 static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
115 clk = clk_register_fixed_rate(NULL, "pll2", NULL, 0, 960000000); in mmp2_clk_init()
116 clk_register_clkdev(clk, "pll2", NULL); in mmp2_clk_init()
150 clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2", in mmp2_clk_init()
166 clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2", in mmp2_clk_init()
/kernel/linux/linux-4.19/drivers/gpu/drm/hisilicon/hibmc/
Dhibmc_drm_de.c285 u32 *pll1, u32 *pll2) in get_pll_config() argument
294 *pll2 = hibmc_pll_table[i].pll2_config_value; in get_pll_config()
301 *pll2 = CRT_PLL2_HS_25MHZ; in get_pll_config()
317 u32 pll2; /* bit[63:32] of PLL */ in display_ctrl_adjust() local
323 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
324 writel(pll2, priv->mmio + CRT_PLL2_HS); in display_ctrl_adjust()
/kernel/linux/linux-4.19/drivers/clk/mmp/
Dclk-mmp2.c72 static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
73 static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
115 clk = clk_register_fixed_rate(NULL, "pll2", NULL, 0, 960000000); in mmp2_clk_init()
116 clk_register_clkdev(clk, "pll2", NULL); in mmp2_clk_init()
150 clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2", in mmp2_clk_init()
166 clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2", in mmp2_clk_init()
/kernel/linux/linux-5.10/drivers/gpu/drm/hisilicon/hibmc/
Dhibmc_drm_de.c285 u32 *pll1, u32 *pll2) in get_pll_config() argument
294 *pll2 = hibmc_pll_table[i].pll2_config_value; in get_pll_config()
301 *pll2 = CRT_PLL2_HS_25MHZ; in get_pll_config()
317 u32 pll2; /* bit[63:32] of PLL */ in display_ctrl_adjust() local
323 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
324 writel(pll2, priv->mmio + CRT_PLL2_HS); in display_ctrl_adjust()
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv04.c208 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; in setPLL_double_highregs() local
214 /* model specific additions to generic pll1 and pll2 set up above */ in setPLL_double_highregs()
218 pll2 = 0; in setPLL_double_highregs()
227 pll2 |= 0x011f; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
266 nvkm_wr32(device, reg2, pll2); in setPLL_double_highregs()
/kernel/linux/linux-4.19/drivers/gpu/drm/tegra/
Dsor.c294 unsigned int pll2; member
1149 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1151 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1159 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1162 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1650 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1652 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1663 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1667 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1673 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
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