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/kernel/linux/linux-5.10/Documentation/userspace-api/media/v4l/
Dext-ctrls-fm-tx.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _fm-tx-controls:
15 .. _fm-tx-control-id:
27 step are driver-specific.
34 to 31 pre-defined programme types.
52 programme-related information or any other text. In these cases,
103 receiver-generated distortion and prevent overmodulation.
107 useconds. Step and range are driver-specific.
111 are driver-specific.
121 range and step are driver-specific.
[all …]
Dext-ctrls-fm-rx.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _fm-rx-controls:
13 .. _fm-rx-control-id:
27 Gets RDS Programme Type field. This encodes up to 31 pre-defined
45 wishes to transmit longer PS names, programme-related information or
70 enum v4l2_deemphasis -
71 Configures the de-emphasis value for reception. A de-emphasis filter
75 values for de-emphasis. Here they are:
79 .. flat-table::
80 :header-rows: 0
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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/phy/
Dapm-xgene-phy.txt1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
7 - compatible : Shall be "apm,xgene-phy".
8 - reg : PHY memory resource is the SDS PHY access resource.
9 - #phy-cells : Shall be 1 as it expects one argument for setting
14 - status : Shall be "ok" if enabled or "disabled" if disabled.
16 - clocks : Reference to the clock entry.
17 - apm,tx-eye-tuning : Manual control to fine tune the capture of the serial
19 Two set of 3-tuple setting for each (up to 3)
22 - apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
[all …]
Dqcom-qusb2-phy.txt7 - compatible: compatible list, contains
8 "qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996,
9 "qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845.
11 - reg: offset and length of the PHY register set.
12 - #phy-cells: must be 0.
14 - clocks: a list of phandles and clock-specifier pairs,
15 one for each entry in clock-names.
16 - clock-names: must be "cfg_ahb" for phy config clock,
20 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
21 - vdda-phy-dpdm-supply: Phandle to 3.1V regulator supply to Dp/Dm port signals.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dapm-xgene-phy.txt1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
7 - compatible : Shall be "apm,xgene-phy".
8 - reg : PHY memory resource is the SDS PHY access resource.
9 - #phy-cells : Shall be 1 as it expects one argument for setting
14 - status : Shall be "ok" if enabled or "disabled" if disabled.
16 - clocks : Reference to the clock entry.
17 - apm,tx-eye-tuning : Manual control to fine tune the capture of the serial
19 Two set of 3-tuple setting for each (up to 3)
22 - apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
[all …]
Dqcom,qusb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Manu Gautam <mgautam@codeaurora.org>
19 - items:
20 - enum:
21 - qcom,ipq8074-qusb2-phy
22 - qcom,msm8996-qusb2-phy
23 - qcom,msm8998-qusb2-phy
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/kernel/linux/linux-5.10/include/linux/phy/
Dphy-dp.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
49 * @pre:
51 * Pre-emphasis levels, as specified by DisplayPort specification, to be
56 unsigned int pre[4]; member
61 * Flag indicating, whether or not to enable spread-spectrum clocking.
88 * and pre-emphasis to requested values. Only lanes specified
/kernel/linux/linux-4.19/drivers/gpu/drm/sti/
Dsti_hdmi_tx3g4c28phy.c1 // SPDX-License-Identifier: GPL-2.0
76 u32 ckpxpll = hdmi->mode.clock * 1000; in sti_hdmi_tx3g4c28phy_start()
114 hdmi->event_received = false; in sti_hdmi_tx3g4c28phy_start()
119 wait_event_interruptible_timeout(hdmi->wait_event, in sti_hdmi_tx3g4c28phy_start()
120 hdmi->event_received == true, in sti_hdmi_tx3g4c28phy_start()
140 * To configure the source termination and pre-emphasis appropriately in sti_hdmi_tx3g4c28phy_start()
166 * Default, power up the serializer with no pre-emphasis or in sti_hdmi_tx3g4c28phy_start()
190 hdmi->event_received = false; in sti_hdmi_tx3g4c28phy_stop()
199 wait_event_interruptible_timeout(hdmi->wait_event, in sti_hdmi_tx3g4c28phy_stop()
200 hdmi->event_received == true, in sti_hdmi_tx3g4c28phy_stop()
/kernel/linux/linux-5.10/drivers/gpu/drm/sti/
Dsti_hdmi_tx3g4c28phy.c1 // SPDX-License-Identifier: GPL-2.0
78 u32 ckpxpll = hdmi->mode.clock * 1000; in sti_hdmi_tx3g4c28phy_start()
116 hdmi->event_received = false; in sti_hdmi_tx3g4c28phy_start()
121 wait_event_interruptible_timeout(hdmi->wait_event, in sti_hdmi_tx3g4c28phy_start()
122 hdmi->event_received == true, in sti_hdmi_tx3g4c28phy_start()
142 * To configure the source termination and pre-emphasis appropriately in sti_hdmi_tx3g4c28phy_start()
168 * Default, power up the serializer with no pre-emphasis or in sti_hdmi_tx3g4c28phy_start()
192 hdmi->event_received = false; in sti_hdmi_tx3g4c28phy_stop()
201 wait_event_interruptible_timeout(hdmi->wait_event, in sti_hdmi_tx3g4c28phy_stop()
202 hdmi->event_received == true, in sti_hdmi_tx3g4c28phy_stop()
/kernel/linux/linux-4.19/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_debugfs.c44 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
46 * --- to get dp configuration
51 * current -- for current video mode
52 * verified --- maximum configuration which pass link training
53 * reported --- DP rx report caps (DPCD register offset 0, 1 2)
54 * preferred --- user force settings
56 * --- set (or force) dp configuration
77 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; in dp_link_settings_read()
78 struct dc_link *link = connector->dc_link; in dp_link_settings_read()
87 return -EINVAL; in dp_link_settings_read()
[all …]
/kernel/linux/linux-5.10/drivers/phy/samsung/
Dphy-exynos-pcie.c1 // SPDX-License-Identifier: GPL-2.0-only
89 exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK); in exynos5440_pcie_phy_init()
92 exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE); in exynos5440_pcie_phy_init()
95 exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0); in exynos5440_pcie_phy_init()
96 exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1); in exynos5440_pcie_phy_init()
99 exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL); in exynos5440_pcie_phy_init()
101 /* set TX Pre-emphasis Level Control for lane 0 to minimum */ in exynos5440_pcie_phy_init()
102 exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL); in exynos5440_pcie_phy_init()
105 exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS); in exynos5440_pcie_phy_init()
106 exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR); in exynos5440_pcie_phy_init()
[all …]
/kernel/linux/linux-4.19/drivers/phy/samsung/
Dphy-exynos-pcie.c92 exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK); in exynos5440_pcie_phy_init()
95 exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE); in exynos5440_pcie_phy_init()
98 exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0); in exynos5440_pcie_phy_init()
99 exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1); in exynos5440_pcie_phy_init()
102 exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL); in exynos5440_pcie_phy_init()
104 /* set TX Pre-emphasis Level Control for lane 0 to minimum */ in exynos5440_pcie_phy_init()
105 exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL); in exynos5440_pcie_phy_init()
108 exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS); in exynos5440_pcie_phy_init()
109 exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR); in exynos5440_pcie_phy_init()
110 exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR); in exynos5440_pcie_phy_init()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/edp/
Dedp_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
20 while (--cnt) { in msm_edp_phy_ready()
21 status = edp_read(phy->base + in msm_edp_phy_ready()
41 edp_write(phy->base + REG_EDP_PHY_CTRL, in msm_edp_phy_ctrl()
46 edp_write(phy->base + REG_EDP_PHY_CTRL, 0x000); in msm_edp_phy_ctrl()
47 edp_write(phy->base + REG_EDP_PHY_GLB_PD_CTL, 0x3f); in msm_edp_phy_ctrl()
48 edp_write(phy->base + REG_EDP_PHY_GLB_CFG, 0x1); in msm_edp_phy_ctrl()
50 edp_write(phy->base + REG_EDP_PHY_GLB_PD_CTL, 0xc0); in msm_edp_phy_ctrl()
54 /* voltage mode and pre emphasis cfg */
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/kernel/linux/linux-5.10/include/sound/
Dak4117.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
27 #define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
28 #define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
29 #define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
30 #define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */
31 #define AK4117_REG_QSUB_SECOND 0x15 /* Q-subcode second */
32 #define AK4117_REG_QSUB_FRAME 0x16 /* Q-subcode frame */
33 #define AK4117_REG_QSUB_ZERO 0x17 /* Q-subcode zero */
34 #define AK4117_REG_QSUB_ABSMIN 0x18 /* Q-subcode absolute minute */
35 #define AK4117_REG_QSUB_ABSSEC 0x19 /* Q-subcode absolute second */
[all …]
Dak4113.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
50 /* Q-subcode address + control */
52 /* Q-subcode track */
54 /* Q-subcode index */
56 /* Q-subcode minute */
58 /* Q-subcode second */
60 /* Q-subcode frame */
62 /* Q-subcode zero */
64 /* Q-subcode absolute minute */
66 /* Q-subcode absolute second */
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/msm/edp/
Dedp_phy.c2 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
28 while (--cnt) { in msm_edp_phy_ready()
29 status = edp_read(phy->base + in msm_edp_phy_ready()
49 edp_write(phy->base + REG_EDP_PHY_CTRL, in msm_edp_phy_ctrl()
54 edp_write(phy->base + REG_EDP_PHY_CTRL, 0x000); in msm_edp_phy_ctrl()
55 edp_write(phy->base + REG_EDP_PHY_GLB_PD_CTL, 0x3f); in msm_edp_phy_ctrl()
56 edp_write(phy->base + REG_EDP_PHY_GLB_CFG, 0x1); in msm_edp_phy_ctrl()
58 edp_write(phy->base + REG_EDP_PHY_GLB_PD_CTL, 0xc0); in msm_edp_phy_ctrl()
62 /* voltage mode and pre emphasis cfg */
65 edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG0, 0x3); in msm_edp_phy_vm_pe_init()
[all …]
/kernel/linux/linux-4.19/include/sound/
Dak4117.h21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
42 #define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
43 #define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
44 #define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
45 #define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */
46 #define AK4117_REG_QSUB_SECOND 0x15 /* Q-subcode second */
47 #define AK4117_REG_QSUB_FRAME 0x16 /* Q-subcode frame */
48 #define AK4117_REG_QSUB_ZERO 0x17 /* Q-subcode zero */
49 #define AK4117_REG_QSUB_ABSMIN 0x18 /* Q-subcode absolute minute */
50 #define AK4117_REG_QSUB_ABSSEC 0x19 /* Q-subcode absolute second */
[all …]
Dak4113.h22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
65 /* Q-subcode address + control */
67 /* Q-subcode track */
69 /* Q-subcode index */
71 /* Q-subcode minute */
73 /* Q-subcode second */
75 /* Q-subcode frame */
77 /* Q-subcode zero */
79 /* Q-subcode absolute minute */
81 /* Q-subcode absolute second */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/tegra/
Ddp.h1 /* SPDX-License-Identifier: MIT */
3 * Copyright (C) 2013-2019 NVIDIA Corporation.
18 * struct drm_dp_link_caps - DP link capabilities
61 * struct drm_dp_link_ops - DP link operations
80 * struct drm_dp_link_train_set - link training settings
81 * @voltage_swing: per-lane voltage swing
82 * @pre_emphasis: per-lane pre-emphasis
83 * @post_cursor: per-lane post-cursor
92 * struct drm_dp_link_train - link training state information
110 * struct drm_dp_link - DP link capabilities and configuration
/kernel/linux/linux-4.19/Documentation/media/uapi/v4l/
Dextended-controls.rst1 .. -*- coding: utf-8; mode: rst -*-
3 .. _extended-controls:
71 it also allows for 64-bit values and pointers to be passed.
75 such as N-dimensional arrays and/or structures. You need to specify the
84 particular, this ioctl gives the dimensions of the N-dimensional array
113 .. code-block:: c
134 .. code-block:: c
144 The 32-bit ``qctrl.id`` value is subdivided into three bit ranges: the
150 non-zero for controls. The range of 0x1000 and up are reserved for
151 driver-specific controls. The macro ``V4L2_CTRL_ID2CLASS(id)`` returns
[all …]
/kernel/linux/linux-5.10/drivers/media/radio/wl128x/
Dfmdrv_common.h1 /* SPDX-License-Identifier: GPL-2.0-only */
129 #define fm_cb(skb) ((struct fm_skb_cb *)(skb->cb))
131 /* FM Channel-8 command message format */
133 __u8 hdr; /* Logical Channel-8 */
142 /* FM Channel-8 event messgage format */
144 __u8 header; /* Logical Channel-8 */
223 #define FM_RX_RSSI_THRESHOLD_MIN -128
231 /* FM RX De-emphasis filter modes */
347 /* FM TX Pre-emphasis filter values */
357 /* Functions exported by FM common sub-module */
/kernel/linux/linux-4.19/drivers/phy/qualcomm/
Dphy-qcom-qusb2.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/nvmem-consumer.h>
23 #include <dt-bindings/phy/phy-qcom-qusb2.h>
93 * if yes, then offset gives index in the reg-layout
111 /* set of registers with offsets different per-PHY */
238 "vdda-pll", "vdda-phy-dpdm",
244 * struct qusb2_phy - structure holding qusb2 phy attributes
262 * @override_preemphasis: PHY should use different pre-amphasis amplitude
263 * @preemphasis_level: Amplitude Pre-Emphasis to be updated in TUNE1 register
264 * @override_preemphasis_width: PHY should use different pre-emphasis duration
[all …]
/kernel/linux/linux-4.19/drivers/media/radio/wl128x/
Dfmdrv_common.h138 #define fm_cb(skb) ((struct fm_skb_cb *)(skb->cb))
140 /* FM Channel-8 command message format */
142 __u8 hdr; /* Logical Channel-8 */
151 /* FM Channel-8 event messgage format */
153 __u8 header; /* Logical Channel-8 */
232 #define FM_RX_RSSI_THRESHOLD_MIN -128
240 /* FM RX De-emphasis filter modes */
356 /* FM TX Pre-emphasis filter values */
366 /* Functions exported by FM common sub-module */
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Dci-hdrc-usb2.txt4 - compatible: should be one of:
5 "fsl,imx23-usb"
6 "fsl,imx27-usb"
7 "fsl,imx28-usb"
8 "fsl,imx6q-usb"
9 "fsl,imx6sl-usb"
10 "fsl,imx6sx-usb"
11 "fsl,imx6ul-usb"
12 "fsl,imx7d-usb"
13 "fsl,imx7ulp-usb"
[all …]
/kernel/linux/linux-5.10/drivers/phy/cadence/
Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
365 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_write()
367 writew(val, ctx->base + offset); in cdns_regmap_write()
375 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_read()
377 *val = readw(ctx->base + offset); in cdns_regmap_read()
387 writel(val, ctx->base + offset); in cdns_regmap_dptx_write()
398 *val = readl(ctx->base + offset); in cdns_regmap_dptx_read()
497 * Structure used to store values of PHY registers for voltage-related
498 * coefficients, for particular voltage swing and pre-emphasis level. Values
[all …]

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