Home
last modified time | relevance | path

Searched +full:redistributor +full:- +full:stride (Results 1 – 19 of 19) sorted by relevance

/kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic-v3.txt5 Software Generated Interrupts (SGI), and Locality-specific Peripheral
10 - compatible : should at least contain "arm,gic-v3".
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode an
21 SPI interrupts are in the range [0-987]. PPI interrupts are in the
22 range [0-15].
31 pointed must be a subnode of the "ppi-partitions" subnode. For
33 this cell must be zero. See the "ppi-partitions" node description
39 - reg : Specifies base physical address(s) and size of the GIC
41 - GIC Distributor interface (GICD)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/sprd/
Dsc9863a.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/clock/sprd,sc9863a-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <2>;
15 #size-cells = <0>;
17 cpu-map {
48 compatible = "arm,cortex-a55";
50 enable-method = "psci";
51 cpu-idle-states = <&CORE_PD>;
56 compatible = "arm,cortex-a55";
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/
Dsdm660.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
11 interrupt-parent = <&intc>;
13 #address-cells = <2>;
14 #size-cells = <2>;
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <19200000>;
23 clock-output-names = "xo_board";
[all …]
Dsdm630.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
20 xo_board: xo-board {
21 compatible = "fixed-clock";
[all …]
Dmsm8998.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/gpio/gpio.h>
12 interrupt-parent = <&intc>;
14 qcom,msm-id = <292 0x0>;
16 #address-cells = <2>;
[all …]
Dmsm8996.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,apr.h>
12 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/
Dhip05.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/hisilicon/
Dhip05.dtsi12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "hisilicon,hip05-d02";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
26 #address-cells = <1>;
27 #size-cells = <0>;
29 cpu-map {
90 compatible = "arm,cortex-a57", "arm,armv8";
[all …]
Dhip06.dtsi12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "hisilicon,hip06-d03";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
26 #address-cells = <1>;
27 #size-cells = <0>;
29 cpu-map {
90 compatible = "arm,cortex-a57", "arm,armv8";
[all …]
Dhip07.dtsi12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "hisilicon,hip07-d05";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
26 #address-cells = <1>;
27 #size-cells = <0>;
29 cpu-map {
273 compatible = "arm,cortex-a72", "arm,armv8";
[all …]
/kernel/linux/linux-5.10/arch/arm64/kvm/vgic/
Dvgic-v3.c1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/irqchip/arm-gic-v3.h>
20 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; in vgic_v3_set_underflow()
22 cpuif->vgic_hcr |= ICH_HCR_UIE; in vgic_v3_set_underflow()
33 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; in vgic_v3_fold_lr_state()
34 struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3; in vgic_v3_fold_lr_state()
35 u32 model = vcpu->kvm->arch.vgic.vgic_model; in vgic_v3_fold_lr_state()
40 cpuif->vgic_hcr &= ~ICH_HCR_UIE; in vgic_v3_fold_lr_state()
42 for (lr = 0; lr < cpuif->used_lrs; lr++) { in vgic_v3_fold_lr_state()
43 u64 val = cpuif->vgic_lr[lr]; in vgic_v3_fold_lr_state()
[all …]
/kernel/linux/linux-4.19/drivers/irqchip/
Dirq-gic-v3.c2 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
33 #include <linux/irqchip/arm-gic-common.h>
34 #include <linux/irqchip/arm-gic-v3.h>
35 #include <linux/irqchip/irq-partition-percpu.h>
42 #include "irq-gic-common.h"
71 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
79 return d->hwirq; in gic_irq()
89 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ in gic_dist_base()
92 if (d->hwirq <= 1023) /* SPI -> dist_base */ in gic_dist_base()
103 count--; in gic_do_wait_for_rwp()
[all …]
/kernel/linux/linux-4.19/virt/kvm/arm/vgic/
Dvgic-v3.c15 #include <linux/irqchip/arm-gic-v3.h>
32 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; in vgic_v3_set_underflow()
34 cpuif->vgic_hcr |= ICH_HCR_UIE; in vgic_v3_set_underflow()
45 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; in vgic_v3_fold_lr_state()
46 struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3; in vgic_v3_fold_lr_state()
47 u32 model = vcpu->kvm->arch.vgic.vgic_model; in vgic_v3_fold_lr_state()
52 cpuif->vgic_hcr &= ~ICH_HCR_UIE; in vgic_v3_fold_lr_state()
54 for (lr = 0; lr < vgic_cpu->used_lrs; lr++) { in vgic_v3_fold_lr_state()
55 u64 val = cpuif->vgic_lr[lr]; in vgic_v3_fold_lr_state()
70 /* Notify fds when the guest EOI'ed a level-triggered IRQ */ in vgic_v3_fold_lr_state()
[all …]
/kernel/linux/linux-5.10/drivers/irqchip/
Dirq-gic-v3.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
23 #include <linux/irqchip/arm-gic-common.h>
24 #include <linux/irqchip/arm-gic-v3.h>
25 #include <linux/irqchip/irq-partition-percpu.h>
32 #include "irq-gic-common.h"
70 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
74 * When security is enabled, non-secure priority values from the (re)distributor
78 * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
84 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/qcom/
Dmsm8996.dtsi1 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
15 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
16 #include <dt-bindings/clock/qcom,rpmcc.h>
21 interrupt-parent = <&intc>;
23 #address-cells = <2>;
24 #size-cells = <2>;
34 reserved-memory {
35 #address-cells = <2>;
[all …]
/kernel/linux/patches/linux-4.19/hi3516dv300_patch/
Dhi3516dv300.patch1 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
3 --- a/arch/arm/Kconfig
5 @@ -330,7 +330,7 @@ config ARCH_MULTIPLATFORM
9 - select AUTO_ZRELADDR
14 @@ -751,6 +751,8 @@ source "arch/arm/mach-highbank/Kconfig"
16 source "arch/arm/mach-hisi/Kconfig"
18 +source "arch/arm/mach-hibvt/Kconfig"
20 source "arch/arm/mach-imx/Kconfig"
22 source "arch/arm/mach-integrator/Kconfig"
23 diff --git a/arch/arm/Makefile b/arch/arm/Makefile
[all …]