| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | mdio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
17 bus. These should follow the generic ethernet-phy.yaml document, or
24 "#address-cells":
27 "#size-cells":
30 reset-gpios:
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| D | ethernet-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
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| D | hisilicon-femac.txt | 4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
13 - resets: should contain the phandle to the MAC reset signal(required) and
14 the PHY reset signal(optional).
15 - reset-names: should contain the reset signal name "mac"(required)
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| D | hisilicon-hix5hd2-gmac.txt | 4 - compatible: should contain one of the following SoC strings:
5 * "hisilicon,hix5hd2-gmac"
6 * "hisilicon,hi3798cv200-gmac"
7 * "hisilicon,hi3516a-gmac"
9 * "hisilicon,hisi-gmac-v1"
10 * "hisilicon,hisi-gmac-v2"
13 - reg: specifies base physical address(s) and size of the device registers.
16 - interrupts: should contain the MAC interrupt.
17 - #address-cells: must be <1>.
18 - #size-cells: must be <0>.
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/ |
| D | mdio.txt | 6 - reset-gpios: One GPIO that control the RESET lines of all PHYs on that MDIO
8 - reset-delay-us: RESET pulse width in microseconds.
13 The 'reset-delay-us' indicates the RESET signal pulse width in microseconds and
15 on all PHY requirements (maximum value of all per-PHY RESET pulse widths).
24 #address-cells = <1>;
25 #size-cells = <0>;
27 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
28 reset-delay-us = <2>;
30 ethphy0: ethernet-phy@1 {
34 ethphy1: ethernet-phy@3 {
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| D | phy.txt | 5 - interrupts : interrupt specifier for the sole interrupt.
6 - reg : The ID number for the phy, usually a small integer
10 - compatible: Compatible list, may contain
11 "ethernet-phy-ieee802.3-c22" or "ethernet-phy-ieee802.3-c45" for
18 form: "ethernet-phy-idAAAA.BBBB" where
19 AAAA - The value of the 16 bit Phy Identifier 1 register as
21 BBBB - The value of the 16 bit Phy Identifier 2 register as
28 - max-speed: Maximum PHY supported speed (10, 100, 1000...)
30 - broken-turn-around: If set, indicates the PHY device does not correctly
33 - enet-phy-lane-swap: If set, indicates the PHY will swap the TX/RX lanes to
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| D | hisilicon-femac.txt | 4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
13 - resets: should contain the phandle to the MAC reset signal(required) and
14 the PHY reset signal(optional).
15 - reset-names: should contain the reset signal name "mac"(required)
[all …]
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| D | hisilicon-hix5hd2-gmac.txt | 4 - compatible: should contain one of the following SoC strings:
5 * "hisilicon,hix5hd2-gmac"
6 * "hisilicon,hi3798cv200-gmac"
7 * "hisilicon,hi3516a-gmac"
9 * "hisilicon,hisi-gmac-v1"
10 * "hisilicon,hisi-gmac-v2"
13 - reg: specifies base physical address(s) and size of the device registers.
16 - interrupts: should contain the MAC interrupt.
17 - #address-cells: must be <1>.
18 - #size-cells: must be <0>.
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/ |
| D | mmc-pwrseq-simple.txt | 4 common properties between various SOC designs. It thus enables us to use the
8 - compatible : contains "mmc-pwrseq-simple".
11 - reset-gpios : contains a list of GPIO specifiers. The reset GPIOs are asserted
13 They will be de-asserted right after the power has been provided to the
15 - clocks : Must contain an entry for the entry in clock-names.
16 See ../clocks/clock-bindings.txt for details.
17 - clock-names : Must include the following entry:
19 - post-power-on-delay-ms : Delay in ms after powering the card and
20 de-asserting the reset-gpios (if any)
21 - power-off-delay-us : Delay in us after asserting the reset-gpios (if any)
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | mmc-pwrseq-simple.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
14 of common properties between various SOC designs. It thus enables us to use
19 const: mmc-pwrseq-simple
21 reset-gpios:
26 contains a list of GPIO specifiers. The reset GPIOs are asserted
28 They will be de-asserted right after the power has been provided to the
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| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | sdhci-bcm-kona.c | 16 #include <linux/delay.h>
25 #include <linux/mmc/slot-gpio.h>
27 #include "sdhci-pltfm.h"
63 /* This timeout should be sufficent for core to reset */ in sdhci_bcm_kona_sd_reset()
66 /* reset the host using the top level reset */ in sdhci_bcm_kona_sd_reset()
73 pr_err("Error: sd host is stuck in reset!!!\n"); in sdhci_bcm_kona_sd_reset()
74 return -EFAULT; in sdhci_bcm_kona_sd_reset()
78 /* bring the host out of reset */ in sdhci_bcm_kona_sd_reset()
83 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS) in sdhci_bcm_kona_sd_reset()
84 * Back-to-Back writes to same register needs delay when SD bus clock in sdhci_bcm_kona_sd_reset()
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| /kernel/linux/linux-4.19/drivers/mmc/host/ |
| D | sdhci-bcm-kona.c | 16 #include <linux/delay.h>
27 #include <linux/mmc/slot-gpio.h>
29 #include "sdhci-pltfm.h"
65 /* This timeout should be sufficent for core to reset */ in sdhci_bcm_kona_sd_reset()
68 /* reset the host using the top level reset */ in sdhci_bcm_kona_sd_reset()
75 pr_err("Error: sd host is stuck in reset!!!\n"); in sdhci_bcm_kona_sd_reset()
76 return -EFAULT; in sdhci_bcm_kona_sd_reset()
80 /* bring the host out of reset */ in sdhci_bcm_kona_sd_reset()
85 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS) in sdhci_bcm_kona_sd_reset()
86 * Back-to-Back writes to same register needs delay when SD bus clock in sdhci_bcm_kona_sd_reset()
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | exynos4412-galaxy-s3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include "exynos4412-midas.dtsi"
20 flen-gpios = <&gpj1 1 GPIO_ACTIVE_HIGH>;
21 enset-gpios = <&gpj1 2 GPIO_ACTIVE_HIGH>;
23 pinctrl-names = "default", "host", "isp";
24 pinctrl-0 = <&camera_flash_host>;
25 pinctrl-1 = <&camera_flash_host>;
26 pinctrl-2 = <&camera_flash_isp>;
28 flash-led {
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| D | rk3288-rock2-som.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/pwm/pwm.h>
12 emmc_pwrseq: emmc-pwrseq {
13 compatible = "mmc-pwrseq-emmc";
14 pinctrl-0 = <&emmc_reset>;
15 pinctrl-names = "default";
16 reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
19 ext_gmac: external-gmac-clock {
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/usb/ |
| D | ci-hdrc-usb2.txt | 4 - compatible: should be one of:
5 "fsl,imx23-usb"
6 "fsl,imx27-usb"
7 "fsl,imx28-usb"
8 "fsl,imx6q-usb"
9 "fsl,imx6sl-usb"
10 "fsl,imx6sx-usb"
11 "fsl,imx6ul-usb"
12 "fsl,imx7d-usb"
13 "lsi,zevio-usb"
[all …]
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| /kernel/linux/linux-5.10/drivers/fpga/ |
| D | ice40-spi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/fpga/fpga-mgr.h>
21 #define ICE40_SPI_RESET_DELAY 1 /* us (>200ns) */
22 #define ICE40_SPI_HOUSEKEEPING_DELAY 1200 /* us */
28 struct gpio_desc *reset; member
34 struct ice40_fpga_priv *priv = mgr->priv; in ice40_fpga_ops_state()
36 return gpiod_get_value(priv->cdone) ? FPGA_MGR_STATE_OPERATING : in ice40_fpga_ops_state()
44 struct ice40_fpga_priv *priv = mgr->priv; in ice40_fpga_ops_write_init()
45 struct spi_device *dev = priv->dev; in ice40_fpga_ops_write_init()
49 .delay = { in ice40_fpga_ops_write_init()
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | exynos4412-galaxy-s3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include "exynos4412-midas.dtsi"
18 lcd_vdd3_reg: voltage-regulator-6 {
19 compatible = "regulator-fixed";
20 regulator-name = "LCD_VDD_2.2V";
21 regulator-min-microvolt = <2200000>;
22 regulator-max-microvolt = <2200000>;
24 enable-active-high;
27 ps_als_reg: voltage-regulator-7 {
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| D | rk3288-rock2-som.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/pwm/pwm.h>
12 emmc_pwrseq: emmc-pwrseq {
13 compatible = "mmc-pwrseq-emmc";
14 pinctrl-0 = <&emmc_reset>;
15 pinctrl-names = "default";
16 reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
19 ext_gmac: external-gmac-clock {
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
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| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/delay.h>
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
46 * H/W requires a 5us delay between disabling the bypass and in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
51 /* De-assert active-low PLL reset. */ in clk_pll_enable()
52 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/rockchip/ |
| D | rk3328-nanopi-r2s.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/gpio/gpio.h>
14 compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
17 stdout-path = "serial2:1500000n8";
20 gmac_clk: gmac-clock {
21 compatible = "fixed-clock";
22 clock-frequency = <125000000>;
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| /kernel/linux/linux-4.19/drivers/clk/qcom/ |
| D | clk-pll.c | 18 #include <linux/delay.h>
20 #include <linux/clk-provider.h>
25 #include "clk-pll.h"
39 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
48 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
54 * H/W requires a 5us delay between disabling the bypass and in clk_pll_enable()
55 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
59 /* De-assert active-low PLL reset. */ in clk_pll_enable()
60 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
69 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_enable()
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| /kernel/linux/linux-4.19/Documentation/blockdev/ |
| D | paride.txt | 4 PARIDE v1.03 (c) 1997-8 Grant Guenther <grant@torque.net>
9 to personal computers, many external devices such as portable hard-disk,
10 CD-ROM, LS-120 and tape drives use the parallel port to connect to their
11 host computer. While some devices (notably scanners) use ad-hoc methods
14 a parallel-port adapter chip added in. Some of the original parallel port
16 (The Iomega PPA-3 adapter used in the ZIP drives is an example of this
24 which is then connected to a floppy-tape mechanism. The vast majority
27 were to open up a parallel port CD-ROM drive, for instance, one would
28 find a standard ATAPI CD-ROM drive, a power supply, and a single adapter
30 IDE cable. It is usually possible to exchange the CD-ROM device with
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/amlogic/ |
| D | meson-gxm-q200.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/input/input.h>
11 #include "meson-gxm.dtsi"
12 #include "meson-gx-p23x-q20x.dtsi"
15 compatible = "amlogic,q200", "amlogic,s912", "amlogic,meson-gxm";
18 adc-keys {
19 compatible = "adc-keys";
20 io-channels = <&saradc 0>;
21 io-channel-names = "buttons";
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| D | meson-gxl-s905d-p230.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/input/input.h>
11 #include "meson-gxl-s905d.dtsi"
12 #include "meson-gx-p23x-q20x.dtsi"
15 compatible = "amlogic,p230", "amlogic,s905d", "amlogic,meson-gxl";
18 adc-keys {
19 compatible = "adc-keys";
20 io-channels = <&saradc 0>;
21 io-channel-names = "buttons";
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| /kernel/linux/linux-5.10/drivers/acpi/ |
| D | reboot.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/delay.h>
14 /* The reset register can only live on bus 0. */ in acpi_pci_reboot()
19 devfn = PCI_DEVFN((rr->address >> 32) & 0xffff, in acpi_pci_reboot()
20 (rr->address >> 16) & 0xffff); in acpi_pci_reboot()
22 /* Write the value that resets us. */ in acpi_pci_reboot()
24 (rr->address & 0xffff), reset_value); in acpi_pci_reboot()
44 /* ACPI reset register was only introduced with v2 of the FADT */ in acpi_reboot()
49 /* Is the reset register supported? The spec says we should be in acpi_reboot()
57 /* The reset register can only exist in I/O, Memory or PCI config space in acpi_reboot()
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