Searched +full:sdhci +full:- +full:8 (Results 1 – 25 of 413) sorted by relevance
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/ |
| D | brcm,sdhci-iproc.txt | 1 Broadcom IPROC SDHCI controller
4 by mmc.txt and the properties that represent the IPROC SDHCI controller.
7 - compatible : Should be one of the following
8 "brcm,bcm2835-sdhci"
9 "brcm,sdhci-iproc-cygnus"
10 "brcm,sdhci-iproc"
12 Use brcm2835-sdhci for Rasperry PI.
14 Use sdhci-iproc-cygnus for Broadcom SDHCI Controllers
15 restricted to 32bit host accesses to SDHCI registers.
17 Use sdhci-iproc for Broadcom SDHCI Controllers that allow standard
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| D | marvell,xenon-sdhci.txt | 1 Marvell Xenon SDHCI Controller device tree bindings
11 - compatible: should be one of the following
12 - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13 Must provide a second register area and marvell,pad-type.
14 - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15 - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
17 - clocks:
22 - clock-names:
27 - reg:
28 * For "marvell,armada-3700-sdhci", two register areas.
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| D | sdhci-pxa.txt | 1 * Marvell sdhci-pxa v2/v3 controller
4 and the properties used by the sdhci-pxav2 and sdhci-pxav3 drivers.
7 - compatible: Should be "mrvl,pxav2-mmc", "mrvl,pxav3-mmc" or
8 "marvell,armada-380-sdhci".
9 - reg:
10 * for "mrvl,pxav2-mmc" and "mrvl,pxav3-mmc", one register area for
11 the SDHCI registers.
13 * for "marvell,armada-380-sdhci", three register areas. The first
14 one for the SDHCI registers themselves, the second one for the
15 AXI/Mbus bridge registers of the SDHCI unit, the third one for the
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| D | nvidia,tegra20-sdhci.txt | 7 by mmc.txt and the properties used by the sdhci-tegra driver.
10 - compatible : should be one of:
11 - "nvidia,tegra20-sdhci": for Tegra20
12 - "nvidia,tegra30-sdhci": for Tegra30
13 - "nvidia,tegra114-sdhci": for Tegra114
14 - "nvidia,tegra124-sdhci": for Tegra124 and Tegra132
15 - "nvidia,tegra210-sdhci": for Tegra210
16 - "nvidia,tegra186-sdhci": for Tegra186
17 - clocks : Must contain one entry, for the module clock.
18 See ../clocks/clock-bindings.txt for details.
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| D | sdhci-st.txt | 1 * STMicroelectronics sdhci-st MMC/SD controller
5 used by the sdhci-st driver.
8 - compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
13 - clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory)
14 See: Documentation/devicetree/bindings/resource-names.txt
15 - clocks: Phandle to the clock.
16 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
18 - interrupts: One mmc interrupt should be described here.
19 - interrupt-names: Should be "mmcirq".
21 - pinctrl-names: A pinctrl state names "default" must be defined.
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| D | arasan,sdhci.txt | 1 Device Tree Bindings for the Arasan SDHCI Controller
7 [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
9 [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
12 - compatible: Compatibility string. One of:
13 - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
14 - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
15 - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
16 - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
17 For this device it is strongly suggested to include arasan,soc-ctl-syscon.
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| D | sdhci-msm.txt | 1 * Qualcomm SDHCI controller (sdhci-msm)
4 and the properties used by the sdhci-msm driver.
7 - compatible: Should contain:
8 "qcom,sdhci-msm-v4" for sdcc versions less than 5.0
9 "qcom,sdhci-msm-v5" for sdcc versions >= 5.0
12 string is added to support this change - "qcom,sdhci-msm-v5".
13 - reg: Base address and length of the register in the following order:
14 - Host controller register map (required)
15 - SD Core register map (required)
16 - interrupts: Should contain an interrupt-specifiers for the interrupts:
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| D | sdhci-of-dwcmshc.txt | 4 - compatible: should be one of the following:
5 "snps,dwcmshc-sdhci"
6 - reg: offset and length of the register set for the device.
7 - interrupts: a single interrupt specifier.
8 - clocks: Array of clocks required for SDHCI; requires at least one for
10 - clock-names: Array of names corresponding to clocks property; shall be
14 sdhci2: sdhci@aa0000 {
15 compatible = "snps,dwcmshc-sdhci";
19 bus-width = <8>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | brcm,sdhci-iproc.txt | 1 Broadcom IPROC SDHCI controller
4 by mmc.txt and the properties that represent the IPROC SDHCI controller.
7 - compatible : Should be one of the following
8 "brcm,bcm2835-sdhci"
9 "brcm,bcm2711-emmc2"
10 "brcm,sdhci-iproc-cygnus"
11 "brcm,sdhci-iproc"
13 Use brcm2835-sdhci for the eMMC controller on the BCM2835 (Raspberry Pi) and
14 bcm2711-emmc2 for the additional eMMC2 controller on BCM2711.
16 Use sdhci-iproc-cygnus for Broadcom SDHCI Controllers
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| D | marvell,xenon-sdhci.txt | 1 Marvell Xenon SDHCI Controller device tree bindings
11 - compatible: should be one of the following
12 - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13 Must provide a second register area and marvell,pad-type.
14 - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15 - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
17 - clocks:
22 - clock-names:
27 - reg:
28 * For "marvell,armada-3700-sdhci", two register areas.
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| D | nvidia,tegra20-sdhci.txt | 7 by mmc.txt and the properties used by the sdhci-tegra driver.
10 - compatible : should be one of:
11 - "nvidia,tegra20-sdhci": for Tegra20
12 - "nvidia,tegra30-sdhci": for Tegra30
13 - "nvidia,tegra114-sdhci": for Tegra114
14 - "nvidia,tegra124-sdhci": for Tegra124 and Tegra132
15 - "nvidia,tegra210-sdhci": for Tegra210
16 - "nvidia,tegra186-sdhci": for Tegra186
17 - "nvidia,tegra194-sdhci": for Tegra194
18 - clocks: For Tegra210, Tegra186 and Tegra194 must contain two entries.
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| D | sdhci-st.txt | 1 * STMicroelectronics sdhci-st MMC/SD controller
5 used by the sdhci-st driver.
8 - compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
13 - clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory)
14 See: Documentation/devicetree/bindings/resource-names.txt
15 - clocks: Phandle to the clock.
16 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
18 - interrupts: One mmc interrupt should be described here.
19 - interrupt-names: Should be "mmcirq".
21 - pinctrl-names: A pinctrl state names "default" must be defined.
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| D | sdhci-msm.txt | 1 * Qualcomm SDHCI controller (sdhci-msm)
4 and the properties used by the sdhci-msm driver.
7 - compatible: Should contain a SoC-specific string and a IP version string:
9 "qcom,sdhci-msm-v4" for sdcc versions less than 5.0
10 "qcom,sdhci-msm-v5" for sdcc version 5.0
13 string is added to support this change - "qcom,sdhci-msm-v5".
15 "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
16 "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
17 "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
18 "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
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| D | aspeed,sdhci.yaml | 1 # SPDX-License-Identifier: GPL-2.0-or-later
4 ---
5 $id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Jeffery <andrew@aj.id.au>
12 - Ryan Chen <ryanchen.aspeed@gmail.com>
16 Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if
26 - aspeed,ast2400-sd-controller
27 - aspeed,ast2500-sd-controller
28 - aspeed,ast2600-sd-controller
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| D | sdhci-pxa.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell PXA SDHCI v2/v3 bindings
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: marvell,armada-380-sdhci
23 reg-names:
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| D | arasan,sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Device Tree Bindings for the Arasan SDHCI Controller
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: "mmc-controller.yaml#"
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
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| D | sdhci-of-dwcmshc.txt | 4 - compatible: should be one of the following:
5 "snps,dwcmshc-sdhci"
6 - reg: offset and length of the register set for the device.
7 - interrupts: a single interrupt specifier.
8 - clocks: Array of clocks required for SDHCI; requires at least one for
10 - clock-names: Array of names corresponding to clocks property; shall be
14 sdhci2: sdhci@aa0000 {
15 compatible = "snps,dwcmshc-sdhci";
19 bus-width = <8>;
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| D | sdhci-sprd.txt | 1 * Spreadtrum SDHCI controller (sdhci-sprd)
7 and the properties used by the sdhci-sprd driver.
10 - compatible: Should contain "sprd,sdhci-r11".
11 - reg: physical base address of the controller and length.
12 - interrupts: Interrupts used by the SDHCI controller.
13 - clocks: Should contain phandle for the clock feeding the SDHCI controller
14 - clock-names: Should contain the following:
15 "sdio" - SDIO source clock (required)
16 "enable" - gate clock which used for enabling/disabling the device (required)
17 "2x_enable" - gate clock controlling the device for some special platforms (optional)
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| D | sdhci-am654.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: mmc-controller.yaml#
19 - ti,am654-sdhci-5.1
20 - ti,j721e-sdhci-8bit
21 - ti,j721e-sdhci-4bit
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | mvebu-gated-clock.txt | 12 -----------------------------------
21 17 sdio SDHCI Host
29 -----------------------------------
35 8 audio Audio Cntrl
40 17 sdio SDHCI Host
56 -----------------------------------
64 8 pex0 PCIe 0
83 -----------------------------------
87 8 pex0 PCIe 0
97 -----------------------------------
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ |
| D | mvebu-gated-clock.txt | 12 -----------------------------------
21 17 sdio SDHCI Host
29 -----------------------------------
35 8 audio Audio Cntrl
40 17 sdio SDHCI Host
56 -----------------------------------
64 8 pex0 PCIe 0
83 -----------------------------------
87 8 pex0 PCIe 0
97 -----------------------------------
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| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | sdhci-s3c.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/mmc/host/sdhci-s3c.c
9 * SDHCI (HSMMC) support for Samsung SoC
14 #include <linux/dma-mapping.h>
16 #include <linux/platform_data/mmc-sdhci-s3c.h>
29 #include "sdhci.h"
63 #define S3C_SDHCI_CTRL2_ENCLKOUTHOLD BIT(8)
86 #define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
87 #define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
88 #define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
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| D | sdhci-st.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support for SDHCI on STMicroelectronics SoCs
9 * Based on sdhci-cns3xxx.c
18 #include "sdhci-pltfm.h"
31 #define ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT BIT(8)
59 #define ST_MMC_CCONFIG_3P3_VOLT BIT(8)
72 #define ST_MMC_CCONFIG_DDR50 BIT(8)
78 #define ST_MMC_CCONFIG_TUNING_FOR_SDR50 BIT(8)
88 #define ST_TOP_MMC_DLY_FIX_OFF(x) (x - 0x8)
97 #define ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE BIT(8)
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| /kernel/linux/linux-4.19/drivers/mmc/host/ |
| D | sdhci-s3c.c | 1 /* linux/drivers/mmc/host/sdhci-s3c.c
8 * SDHCI (HSMMC) support for Samsung SoC
17 #include <linux/dma-mapping.h>
19 #include <linux/platform_data/mmc-sdhci-s3c.h>
32 #include "sdhci.h"
66 #define S3C_SDHCI_CTRL2_ENCLKOUTHOLD BIT(8)
89 #define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
90 #define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
91 #define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
107 * struct sdhci_s3c - S3C SDHCI instance
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| D | sdhci-st.c | 2 * Support for SDHCI on STMicroelectronics SoCs
8 * Based on sdhci-cns3xxx.c
27 #include "sdhci-pltfm.h"
40 #define ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT BIT(8)
68 #define ST_MMC_CCONFIG_3P3_VOLT BIT(8)
81 #define ST_MMC_CCONFIG_DDR50 BIT(8)
87 #define ST_MMC_CCONFIG_TUNING_FOR_SDR50 BIT(8)
97 #define ST_TOP_MMC_DLY_FIX_OFF(x) (x - 0x8)
106 #define ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE BIT(8)
111 /* register to provide the phase-shift value for DLL */
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