| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,nsp-cpu-method.txt | 2 ---------------------------------------------
3 This binding defines the enable method used for starting secondary
8 properties in the corresponding secondary "cpu" device tree node:
9 - enable-method = "brcm,bcm-nsp-smp";
10 - secondary-boot-reg = <...>;
12 The secondary-boot-reg property is a u32 value that specifies the
14 entry point for a secondary CPU. This entry is cpu node specific
21 #address-cells = <1>;
22 #size-cells = <0>;
26 compatible = "arm,cortex-a9";
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| D | brcm,bcm23550-cpu-method.txt | 2 --------------------------------------
3 This binding defines the enable method used for starting secondary
9 - enable-method = "brcm,bcm23550";
10 - secondary-boot-reg = <...>;
12 The secondary-boot-reg property is a u32 value that specifies the
14 code release a secondary CPU. The value written to the register is
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a9";
26 reg = <0>;
[all …]
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| D | brcm,bcm11351-cpu-method.txt | 2 --------------------------------------
3 This binding defines the enable method used for starting secondary
9 - enable-method = "brcm,bcm11351-cpu-method";
10 - secondary-boot-reg = <...>;
12 The secondary-boot-reg property is a u32 value that specifies the
14 code release a secondary CPU. The value written to the register is
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a9";
26 reg = <0>;
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| D | brcm,bcm63138.txt | 1 Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
2 -----------------------------------------------------------
4 Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
11 An optional Boot lookup table Device Tree node is required for secondary CPU
13 defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
14 'enable-method' property.
16 Required properties for the Boot lookup table node:
17 - compatible: should be "brcm,bcm63138-bootlut"
18 - reg: register base address and length for the Boot Lookup table
21 - enable-method: should be "brcm,bcm63138"
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,bcm63138.txt | 1 Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
2 -----------------------------------------------------------
4 Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
11 An optional Boot lookup table Device Tree node is required for secondary CPU
13 defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
14 'enable-method' property.
16 Required properties for the Boot lookup table node:
17 - compatible: should be "brcm,bcm63138-bootlut"
18 - reg: register base address and length for the Boot Lookup table
21 - enable-method: should be "brcm,bcm63138"
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-bcm/ |
| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2015 Broadcom Corporation
12 #include <linux/irqchip/irq-bcm2836.h>
33 /* Name of device node property defining secondary boot register location */
34 #define OF_SECONDARY_BOOT "secondary-boot-reg"
54 return -ENXIO; in scu_a9_enable()
61 return -ENOENT; in scu_a9_enable()
68 return -ENOMEM; in scu_a9_enable()
91 pr_err("required secondary boot register not specified for CPU%u\n", in secondary_boot_addr_for()
106 return -EINVAL; in nsp_write_lut()
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| /kernel/linux/linux-4.19/arch/arm/mach-bcm/ |
| D | platsmp.c | 2 * Copyright (C) 2014-2015 Broadcom Corporation
20 #include <linux/irqchip/irq-bcm2836.h>
39 /* Name of device node property defining secondary boot register location */
40 #define OF_SECONDARY_BOOT "secondary-boot-reg"
60 return -ENXIO; in scu_a9_enable()
67 return -ENOENT; in scu_a9_enable()
74 return -ENOMEM; in scu_a9_enable()
97 pr_err("required secondary boot register not specified for CPU%u\n", in secondary_boot_addr_for()
112 return -EINVAL; in nsp_write_lut()
117 pr_warn("unable to ioremap SKU-ROM LUT register for cpu %u\n", cpu); in nsp_write_lut()
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/ |
| D | xpedite5301.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "PMC/XMC";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
28 #address-cells = <1>;
29 #size-cells = <0>;
33 reg = <0x0>;
34 d-cache-line-size = <32>; // 32 bytes
[all …]
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| D | xpedite5330.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "3U CompactPCI";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #address-cells = <1>;
30 #size-cells = <0>;
33 cell-index = <0>;
37 * module-present;
[all …]
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| D | xpedite5370.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * XPedite5370 3U VPX single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
26 #address-cells = <1>;
27 #size-cells = <0>;
31 reg = <0x0>;
32 d-cache-line-size = <32>; // 32 bytes
33 i-cache-line-size = <32>; // 32 bytes
[all …]
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| D | xcalibur1501.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 reg = <0x0>;
33 d-cache-line-size = <32>; // 32 bytes
34 i-cache-line-size = <32>; // 32 bytes
[all …]
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| /kernel/linux/linux-4.19/arch/powerpc/boot/dts/ |
| D | xpedite5301.dts | 12 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
18 form-factor = "PMC/XMC";
19 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
31 #address-cells = <1>;
32 #size-cells = <0>;
36 reg = <0x0>;
37 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <32>; // 32 bytes
[all …]
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| D | xpedite5330.dts | 12 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
18 form-factor = "3U CompactPCI";
19 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
32 #address-cells = <1>;
33 #size-cells = <0>;
36 cell-index = <0>;
40 * module-present;
46 #address-cells = <1>;
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| D | xpedite5370.dts | 5 * XPedite5370 3U VPX single-board computer based on MPC8572E
12 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
29 #address-cells = <1>;
30 #size-cells = <0>;
34 reg = <0x0>;
35 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
[all …]
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| D | xcalibur1501.dts | 5 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
12 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
30 #address-cells = <1>;
31 #size-cells = <0>;
35 reg = <0x0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
[all …]
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| /kernel/linux/linux-4.19/arch/arm64/kernel/ |
| D | smp.c | 71 * so we need some other way of telling a new secondary core
93 return -ENOSYS; in op_cpu_kill()
99 * Boot a secondary CPU, and assign it the specified idle task.
104 if (cpu_ops[cpu]->cpu_boot) in boot_secondary()
105 return cpu_ops[cpu]->cpu_boot(cpu); in boot_secondary()
107 return -EOPNOTSUPP; in boot_secondary()
119 * We need to tell the secondary core where to find its stack and the in __cpu_up()
143 pr_crit("CPU%u: does not support 52-bit VAs\n", cpu); in __cpu_up()
145 ret = -EIO; in __cpu_up()
148 pr_err("CPU%u: failed to boot: %d\n", cpu, ret); in __cpu_up()
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| /kernel/linux/linux-4.19/arch/arm/mach-qcom/ |
| D | platsmp.c | 61 * Synchronise with the boot thread. in qcom_secondary_init()
72 node = of_find_compatible_node(NULL, NULL, "qcom,gcc-msm8660"); in scss_release_secondary()
75 return -ENXIO; in scss_release_secondary()
81 return -ENOMEM; in scss_release_secondary()
95 void __iomem *reg, *saw_reg; in kpssv1_release_secondary() local
101 return -ENODEV; in kpssv1_release_secondary()
105 ret = -ENODEV; in kpssv1_release_secondary()
111 ret = -ENODEV; in kpssv1_release_secondary()
115 reg = of_iomap(acc_node, 0); in kpssv1_release_secondary()
116 if (!reg) { in kpssv1_release_secondary()
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| /kernel/linux/linux-5.10/arch/arm64/kernel/ |
| D | smp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
27 #include <linux/irqchip/arm-gic-v3.h>
62 * so we need some other way of telling a new secondary core
92 return -ENOSYS; in op_cpu_kill()
98 * Boot a secondary CPU, and assign it the specified idle task.
105 if (ops->cpu_boot) in boot_secondary()
106 return ops->cpu_boot(cpu); in boot_secondary()
108 return -EOPNOTSUPP; in boot_secondary()
119 * We need to tell the secondary core where to find its stack and the in __cpu_up()
130 pr_err("CPU%u: failed to boot: %d\n", cpu, ret); in __cpu_up()
[all …]
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| D | cpufeature.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * there's a little bit of over-abstraction that tends to obscure what's going
14 * user-visible instructions are available only on a subset of the available
16 * boot CPU and comparing these with the feature registers of each secondary
18 * snapshot state to indicate the lowest-common denominator of the feature,
31 * - Mismatched features are *always* sanitised to a "safe" value, which
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/openrisc/opencores/ |
| D | or1ksim.txt | 6 specification, however some aspects, such as the boot protocol have been defined
10 -------------------
11 - compatible: Must include "opencores,or1ksim"
14 ----------
16 - #address-cells: Must be 1.
17 - #size-cells: Must be 0.
18 A CPU sub-node is also required for at least CPU 0. Since the topology may
19 be probed via CPS, it is not necessary to specify secondary CPUs. Required
21 - compatible: Must be "opencores,or1200-rtlsvn481".
22 - reg: CPU number.
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/openrisc/opencores/ |
| D | or1ksim.txt | 6 specification, however some aspects, such as the boot protocol have been defined
10 -------------------
11 - compatible: Must include "opencores,or1ksim"
14 ----------
16 - #address-cells: Must be 1.
17 - #size-cells: Must be 0.
18 A CPU sub-node is also required for at least CPU 0. Since the topology may
19 be probed via CPS, it is not necessary to specify secondary CPUs. Required
21 - compatible: Must be "opencores,or1200-rtlsvn481".
22 - reg: CPU number.
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | bcm23550.dtsi | 33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
37 #include "dt-bindings/clock/bcm21664.h"
40 #address-cells = <1>;
41 #size-cells = <1>;
44 interrupt-parent = <&gic>;
47 #address-cells = <1>;
48 #size-cells = <0>;
52 compatible = "arm,cortex-a7";
53 reg = <0>;
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| D | bcm4708.dtsi | 5 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
20 stdout-path = "serial0:115200n8";
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "brcm,bcm-nsp-smp";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
32 reg = <0x0>;
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | bcm23550.dtsi | 33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
37 #include "dt-bindings/clock/bcm21664.h"
44 interrupt-parent = <&gic>;
47 #address-cells = <1>;
48 #size-cells = <0>;
52 compatible = "arm,cortex-a7";
53 reg = <0>;
54 clock-frequency = <1000000000>;
59 compatible = "arm,cortex-a7";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
42 reg:
54 Bits [11:0] in the reg cell must be set to
57 All other bits in the reg cell must be set to 0.
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