Home
last modified time | relevance | path

Searched +full:smmu +full:- +full:v2 (Results 1 – 25 of 35) sorted by relevance

12

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iommu/
Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
18 The SMMU may also raise interrupts in response to various fault
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/iommu/
Darm,smmu.txt7 The SMMU may also raise interrupts in response to various fault
12 - compatible : Should be one of:
14 "arm,smmu-v1"
15 "arm,smmu-v2"
16 "arm,mmu-400"
17 "arm,mmu-401"
18 "arm,mmu-500"
19 "cavium,smmu-v2"
24 - reg : Base address and size of the SMMU.
26 - #global-interrupts : The number of global interrupts exposed by the
[all …]
/kernel/linux/linux-4.19/drivers/iommu/
Darm-smmu.c2 * IOMMU API for ARM architected SMMU implementations.
15 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * - SMMUv1 and v2 implementations
23 * - Stream-matching and stream-indexing
24 * - v7/v8 long-descriptor format
25 * - Non-secure access to the SMMU
26 * - Context fault reporting
27 * - Extended Stream ID (16 bit)
30 #define pr_fmt(fmt) "arm-smmu: " fmt
36 #include <linux/dma-iommu.h>
[all …]
Darm-smmu-v3.c29 #include <linux/dma-iommu.h>
45 #include "io-pgtable.h"
114 /* CR1 cacheability fields don't quite follow the usual TCR-style encoding */
193 #define Q_IDX(q, p) ((p) & ((1 << (q)->max_n_shift) - 1))
194 #define Q_WRP(q, p) ((p) & (1 << (q)->max_n_shift))
197 #define Q_ENT(q, p) ((q)->base + \
198 Q_IDX(q, p) * (q)->ent_dwords)
262 /* Context descriptor (stage-1 only) */
296 /* Convert between AArch64 (CPU) TCR format and SMMU CD format */
362 /* High-level queue structures */
[all …]
Dqcom_iommu.c2 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c
23 #include <linux/dma-iommu.h>
24 #include <linux/dma-mapping.h>
28 #include <linux/io-64-nonatomic-hi-lo.h>
45 #include "io-pgtable.h"
46 #include "arm-smmu-regs.h"
61 struct qcom_iommu_ctx *ctxs[0]; /* indexed by asid-1 */
89 if (!fwspec || fwspec->ops != &qcom_iommu_ops) in to_iommu()
91 return fwspec->iommu_priv; in to_iommu()
99 return qcom_iommu->ctxs[asid - 1]; in to_ctx()
[all …]
Dmsm_iommu.c1 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
15 * 02110-1301, USA.
36 #include "msm_iommu_hw-8xxx.h"
38 #include "io-pgtable.h"
70 ret = clk_enable(iommu->pclk); in __enable_clocks()
74 if (iommu->clk) { in __enable_clocks()
75 ret = clk_enable(iommu->clk); in __enable_clocks()
77 clk_disable(iommu->pclk); in __enable_clocks()
85 if (iommu->clk) in __disable_clocks()
86 clk_disable(iommu->clk); in __disable_clocks()
[all …]
/kernel/linux/linux-5.10/drivers/iommu/arm/arm-smmu/
Darm-smmu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for ARM architected SMMU implementations.
10 * - SMMUv1 and v2 implementations
11 * - Stream-matching and stream-indexing
12 * - v7/v8 long-descriptor format
13 * - Non-secure access to the SMMU
14 * - Context fault reporting
15 * - Extended Stream ID (16 bit)
18 #define pr_fmt(fmt) "arm-smmu: " fmt
24 #include <linux/dma-iommu.h>
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/
Dsdm630.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
20 xo_board: xo-board {
21 compatible = "fixed-clock";
[all …]
Dmsm8996.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,apr.h>
12 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
[all …]
Dmsm8998.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/gpio/gpio.h>
12 interrupt-parent = <&intc>;
14 qcom,msm-id = <292 0x0>;
16 #address-cells = <2>;
[all …]
/kernel/linux/linux-5.10/drivers/iommu/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 # The IOVA library may also be used by non-IOMMU_API users
6 # The IOASID library may also be used by non-IOMMU_API users
39 sizes at both stage-1 and stage-2, as well as address spaces
40 up to 48-bits in size.
46 Enable self-tests for LPAE page table allocator. This performs
47 a series of page-table consistency checks during boot.
56 Enable support for the ARM Short-descriptor pagetable format.
57 This supports 32-bit virtual and physical addresses mapped using
58 2-level tables with 4KB pages/1MB sections, and contiguous entries
[all …]
/kernel/linux/linux-5.10/drivers/iommu/arm/arm-smmu-v3/
Darm-smmu-v3.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/dma-iommu.h>
20 #include <linux/io-pgtable.h>
29 #include <linux/pci-ats.h>
34 #include "arm-smmu-v3.h"
39 …domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
44 "Disable MSI-based polling for CMD_SYNC completion.");
80 { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },
81 { ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium,cn9900-broken-page1-regspace"},
86 struct arm_smmu_device *smmu) in arm_smmu_page1_fixup() argument
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/
Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/hisilicon/
Dhip07.dtsi12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "hisilicon,hip07-d05";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
26 #address-cells = <1>;
27 #size-cells = <0>;
29 cpu-map {
273 compatible = "arm,cortex-a72", "arm,armv8";
[all …]
Dhip06.dtsi12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "hisilicon,hip06-d03";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
26 #address-cells = <1>;
27 #size-cells = <0>;
29 cpu-map {
90 compatible = "arm,cortex-a57", "arm,armv8";
[all …]
/kernel/linux/linux-5.10/drivers/memory/tegra/
Dmc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
24 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
27 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
30 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
33 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
36 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
39 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
51 spin_lock_irqsave(&mc->lock, flags); in tegra_mc_block_dma_common()
53 value = mc_readl(mc, rst->control) | BIT(rst->bit); in tegra_mc_block_dma_common()
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/intel/
Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/agilex-clock.h>
12 compatible = "intel,socfpga-agilex";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/altera/
Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/kernel/linux/linux-4.19/drivers/memory/tegra/
Dmc.c54 { .compatible = "nvidia,tegra20-mc", .data = &tegra20_mc_soc },
57 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
60 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
63 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
66 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
69 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
81 spin_lock_irqsave(&mc->lock, flags); in terga_mc_block_dma_common()
83 value = mc_readl(mc, rst->control) | BIT(rst->bit); in terga_mc_block_dma_common()
84 mc_writel(mc, value, rst->control); in terga_mc_block_dma_common()
86 spin_unlock_irqrestore(&mc->lock, flags); in terga_mc_block_dma_common()
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/
Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/broadcom/stingray/
Dstingray.dtsi4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 interrupt-parent = <&gic>;
38 #address-cells = <2>;
39 #size-cells = <2>;
42 #address-cells = <2>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a72", "arm,armv8";
49 enable-method = "psci";
50 next-level-cache = <&CLUSTER0_L2>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/broadcom/stingray/
Dstingray.dtsi4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 interrupt-parent = <&gic>;
38 #address-cells = <2>;
39 #size-cells = <2>;
42 #address-cells = <2>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a72";
49 enable-method = "psci";
50 next-level-cache = <&CLUSTER0_L2>;
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2015, Xilinx, Inc.
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "arm,cortex-a53", "arm,armv8";
27 enable-method = "psci";
28 operating-points-v2 = <&cpu_opp_table>;
30 cpu-idle-states = <&CPU_SLEEP_0>;
[all …]
/kernel/linux/linux-5.10/drivers/perf/
Darm_smmuv3_pmu.c1 // SPDX-License-Identifier: GPL-2.0
9 * <phys_addr_page> is the physical page address of the SMMU PMCG wrapped
15 * filter_enable - 0 = no filtering, 1 = filtering enabled
16 * filter_span - 0 = exact match, 1 = pattern match
17 * filter_stream_id - pattern to filter against
19 * To match a partial StreamID where the X most-significant bits must match
20 * but the Y least-significant bits might differ, STREAMID is programmed
22 * STREAMID[Y - 1] == 0.
23 * STREAMID[Y - 2:0] == 1 (where Y > 1).
27 * Example: perf stat -e smmuv3_pmcg_ff88840/transaction,filter_enable=1,
[all …]

12