| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sram/ |
| D | sram.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
15 Each child of the sram node specifies a region of reserved memory. Each
19 Following the generic-names recommended practice, node names should
25 pattern: "^sram(@.*)?"
30 - mmio-sram
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/amlogic/ |
| D | smp-sram.txt | 1 Amlogic Meson8 and Meson8b SRAM for smp bringup:
2 ------------------------------------------------
4 Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
8 Therefore a reserved section sub-node has to be added to the mmio-sram
11 Required sub-node properties:
12 - compatible : depending on the SoC this should be one of:
13 "amlogic,meson8-smp-sram"
14 "amlogic,meson8b-smp-sram"
16 The rest of the properties should follow the generic mmio-sram discription
17 found in ../../misc/sram.txt
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/sram/ |
| D | rockchip-smp-sram.txt | 1 Rockchip SRAM for smp bringup:
2 ------------------------------
4 Rockchip's smp-capable SoCs use the first part of the sram for the bringup
6 residing at the very beginning of the sram.
8 Therefore a reserved section sub-node has to be added to the mmio-sram
11 Required sub-node properties:
12 - compatible : should be "rockchip,rk3066-smp-sram"
14 The rest of the properties should follow the generic mmio-sram discription
15 found in Documentation/devicetree/bindings/sram/sram.txt
19 sram: sram@10080000 {
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| D | renesas,smp-sram.txt | 1 * Renesas SMP SRAM
3 Renesas R-Car Gen2 and RZ/G1 SoCs need a small piece of SRAM for the jump stub
5 This memory is reserved by adding a child node to a "mmio-sram" node, cfr.
6 Documentation/devicetree/bindings/sram/sram.txt.
9 - compatible: Must be "renesas,smp-sram",
10 - reg: Address and length of the reserved SRAM.
16 icram1: sram@e63c0000 {
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
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| D | samsung-sram.txt | 1 Samsung Exynos SYSRAM for SMP bringup:
2 ------------------------------------
4 Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
8 Therefore reserved section sub-nodes have to be added to the mmio-sram
10 non-secure execution environment.
12 Required sub-node properties:
13 - compatible : depending upon boot mode, should be
14 "samsung,exynos4210-sysram" : for Secure SYSRAM
15 "samsung,exynos4210-sysram-ns" : for Non-secure SYSRAM
17 The rest of the properties should follow the generic mmio-sram discription
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| D | sram.txt | 1 Generic on-chip SRAM
7 - compatible : mmio-sram or atmel,sama5d2-securam
9 - reg : SRAM iomem address range
11 Reserving sram areas:
12 ---------------------
14 Each child of the sram node specifies a region of reserved memory. Each
18 Following the generic-names recommended practice, node names should
22 Required properties in the sram node:
24 - #address-cells, #size-cells : should use the same values as the root node
25 - ranges : standard definition, should translate from local addresses
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/sunxi/ |
| D | smp-sram.txt | 1 Allwinner SRAM for smp bringup:
2 ------------------------------------------------
4 Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
9 Therefore a reserved section sub-node has to be added to the mmio-sram
12 Note that this is separate from the Allwinner SRAM controller found in
13 ../../sram/sunxi-sram.txt. This SRAM is secure only and not mappable to
16 Also there are no "secure-only" properties. The implementation should
17 check if this SRAM is usable first.
19 Required sub-node properties:
20 - compatible : depending on the SoC this should be one of:
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| /kernel/linux/linux-5.10/arch/arm/mach-shmobile/ |
| D | pm-rcar-gen2.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Generation 2 Power management support
5 * Copyright (C) 2013 - 2015 Renesas Electronics Corporation
14 #include <linux/smp.h>
18 #include "rcar-gen2.h"
33 #define CA15RESCNT_CPUS 0xf /* CPU0-3 */
35 #define CA7RESCNT_CPUS 0xf /* CPU0-3 */
37 /* On-chip RAM */
60 if (of_device_is_compatible(np, "arm,cortex-a15")) in rcar_gen2_pm_init()
62 else if (of_device_is_compatible(np, "arm,cortex-a7")) in rcar_gen2_pm_init()
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/omap/ |
| D | mpu.txt | 1 * TI - MPU (Main Processor Unit) subsystem
8 - compatible : Should be "ti,omap3-mpu" for OMAP3
9 Should be "ti,omap4-mpu" for OMAP4
10 Should be "ti,omap5-mpu" for OMAP5
11 - ti,hwmods: "mpu"
14 - sram: Phandle to the ocmcram node
17 - pm-sram: Phandles to ocmcram nodes to be used for power management.
18 First should be type 'protect-exec' for the driver to use to copy
20 data region for code. See Documentation/devicetree/bindings/sram/sram.txt
25 - For an OMAP5 SMP system:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/omap/ |
| D | mpu.txt | 1 * TI - MPU (Main Processor Unit) subsystem
8 - compatible : Should be "ti,omap3-mpu" for OMAP3
9 Should be "ti,omap4-mpu" for OMAP4
10 Should be "ti,omap5-mpu" for OMAP5
11 - ti,hwmods: "mpu"
14 - sram: Phandle to the ocmcram node
17 - pm-sram: Phandles to ocmcram nodes to be used for power management.
18 First should be type 'protect-exec' for the driver to use to copy
20 data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
25 - For an OMAP5 SMP system:
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| /kernel/linux/linux-4.19/arch/arm/mach-shmobile/ |
| D | pm-rcar-gen2.c | 2 * R-Car Generation 2 Power management support
4 * Copyright (C) 2013 - 2015 Renesas Electronics Corporation
17 #include <linux/smp.h>
21 #include "rcar-gen2.h"
36 #define CA15RESCNT_CPUS 0xf /* CPU0-3 */
38 #define CA7RESCNT_CPUS 0xf /* CPU0-3 */
40 /* On-chip RAM */
67 if (of_device_is_compatible(np, "arm,cortex-a15")) in rcar_gen2_pm_init()
69 else if (of_device_is_compatible(np, "arm,cortex-a7")) in rcar_gen2_pm_init()
73 np = of_find_compatible_node(NULL, NULL, "renesas,smp-sram"); in rcar_gen2_pm_init()
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| /kernel/linux/linux-5.10/arch/arm/mach-rockchip/ |
| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/smp.h>
57 np = dev->of_node; in rockchip_get_core_reset()
92 ret = -1; in pmu_set_power_domain()
121 pr_err("%s: sram or pmu missing for cpu boot\n", __func__); in rockchip_boot_secondary()
122 return -ENXIO; in rockchip_boot_secondary()
128 return -ENXIO; in rockchip_boot_secondary()
146 * (e.g: cpu frequency, bootrom frequency, sram frequency, ...) in rockchip_boot_secondary()
159 * rockchip_smp_prepare_sram - populate necessary sram block
160 * Starting cores execute the code residing at the start of the on-chip sram
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| /kernel/linux/linux-4.19/arch/arm/mach-rockchip/ |
| D | platsmp.c | 18 #include <linux/smp.h>
66 np = dev->of_node; in rockchip_get_core_reset()
101 ret = -1; in pmu_set_power_domain()
130 pr_err("%s: sram or pmu missing for cpu boot\n", __func__); in rockchip_boot_secondary()
131 return -ENXIO; in rockchip_boot_secondary()
137 return -ENXIO; in rockchip_boot_secondary()
155 * (e.g: cpu frequency, bootrom frequency, sram frequency, ...) in rockchip_boot_secondary()
168 * rockchip_smp_prepare_sram - populate necessary sram block
169 * Starting cores execute the code residing at the start of the on-chip sram
170 * after power-on. Therefore make sure, this sram region is reserved and
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | milbeaut-m10v.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/irq.h>
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
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| D | exynos54xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
28 arm_a7_pmu: arm-a7-pmu {
29 compatible = "arm,cortex-a7-pmu";
30 interrupt-parent = <&gic>;
38 arm_a15_pmu: arm-a15-pmu {
39 compatible = "arm,cortex-a15-pmu";
40 interrupt-parent = <&combiner>;
49 compatible = "arm,armv7-timer";
54 clock-frequency = <24000000>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-meson/ |
| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <linux/smp.h>
23 #define MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(c) (0x04 + ((c - 1) << 2))
31 #define MESON_CPU_PWR_A9_MEM_PD0_M(c) (0x0f << (32 - (c * 4)))
66 /* SMP SRAM */ in meson_smp_prepare_cpus()
69 pr_err("Missing SRAM node\n"); in meson_smp_prepare_cpus()
75 pr_err("Couldn't map SRAM registers\n"); in meson_smp_prepare_cpus()
104 meson_smp_prepare_cpus("arm,cortex-a5-scu", "amlogic,meson8b-pmu", in meson8b_smp_prepare_cpus()
105 "amlogic,meson8b-smp-sram"); in meson8b_smp_prepare_cpus()
110 meson_smp_prepare_cpus("arm,cortex-a9-scu", "amlogic,meson8-pmu", in meson8_smp_prepare_cpus()
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| /kernel/linux/linux-4.19/arch/arm/mach-meson/ |
| D | platsmp.c | 24 #include <linux/smp.h>
33 #define MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(c) (0x04 + ((c - 1) << 2))
41 #define MESON_CPU_PWR_A9_MEM_PD0_M(c) (0x0f << (32 - (c * 4)))
76 /* SMP SRAM */ in meson_smp_prepare_cpus()
79 pr_err("Missing SRAM node\n"); in meson_smp_prepare_cpus()
85 pr_err("Couldn't map SRAM registers\n"); in meson_smp_prepare_cpus()
114 meson_smp_prepare_cpus("arm,cortex-a5-scu", "amlogic,meson8b-pmu", in meson8b_smp_prepare_cpus()
115 "amlogic,meson8b-smp-sram"); in meson8b_smp_prepare_cpus()
120 meson_smp_prepare_cpus("arm,cortex-a9-scu", "amlogic,meson8-pmu", in meson8_smp_prepare_cpus()
121 "amlogic,meson8-smp-sram"); in meson8_smp_prepare_cpus()
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| /kernel/linux/linux-5.10/drivers/soc/renesas/ |
| D | r9a06g032-smp.c | 1 // SPDX-License-Identifier: GPL-2.0
8 * Derived from actions,s500-smp
14 #include <linux/smp.h>
20 * So the default value of the "cpu-release-addr" corresponds to BOOTADDR...
25 * So for NONSEC mode, the bootloader re-parks the second CPU into a pen
26 * in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address,
39 return -ENODEV; in r9a06g032_smp_boot_secondary()
54 int ret = -EINVAL, dns; in r9a06g032_smp_prepare_cpus()
67 if (of_find_property(dn, "cpu-release-addr", &dns)) { in r9a06g032_smp_prepare_cpus()
72 "cpu-release-addr", &temp); in r9a06g032_smp_prepare_cpus()
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| /kernel/linux/linux-4.19/drivers/soc/renesas/ |
| D | r9a06g032-smp.c | 1 // SPDX-License-Identifier: GPL-2.0
8 * Derived from actions,s500-smp
14 #include <linux/smp.h>
20 * So the default value of the "cpu-release-addr" corresponds to BOOTADDR...
25 * So for NONSEC mode, the bootloader re-parks the second CPU into a pen
26 * in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address,
39 return -ENODEV; in r9a06g032_smp_boot_secondary()
54 int ret = -EINVAL, dns; in r9a06g032_smp_prepare_cpus()
67 if (of_find_property(dn, "cpu-release-addr", &dns)) { in r9a06g032_smp_prepare_cpus()
72 "cpu-release-addr", &temp); in r9a06g032_smp_prepare_cpus()
[all …]
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| /kernel/linux/linux-5.10/arch/csky/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
104 For SMP, CPU needs "ldex&stex" instructions for atomic operations.
119 In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not.
162 # VA_BITS - PAGE_SHIFT - 3
196 prompt "C-SKY PMU type"
226 bool "Tightly-Coupled/Sram Memory"
229 The implementation are not only used by TCM (Tightly-Coupled Meory)
230 but also used by sram on SOC bus. It follow existed linux tcm
232 re-used directly.
275 config SMP config
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/hisilicon/ |
| D | hisilicon.txt | 2 ----------------------------------------------------
5 - compatible = "hisilicon,hi3660";
9 - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
13 - compatible = "hisilicon,hi3798cv200";
17 - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
21 - compatible = "hisilicon,hi3620-hi4511";
25 - compatible = "hisilicon,hi6220";
29 - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
33 - compatible = "hisilicon,hip01-ca9x2";
37 - compatible = "hisilicon,hip04-d01";
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | meson8.dtsi | 4 * This file is dual-licensed: you can use it either under the terms
46 #include <dt-bindings/clock/meson8b-clkc.h>
47 #include <dt-bindings/gpio/meson8-gpio.h>
48 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
49 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
57 #address-cells = <1>;
58 #size-cells = <0>;
62 compatible = "arm,cortex-a9";
63 next-level-cache = <&L2>;
65 enable-method = "amlogic,meson8-smp";
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| D | r8a77470.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a7";
24 clock-frequency = <1000000000>;
[all …]
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| D | meson8b.dtsi | 5 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/clock/meson8b-clkc.h>
48 #include <dt-bindings/gpio/meson8b-gpio.h>
49 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
50 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
55 #address-cells = <1>;
56 #size-cells = <0>;
60 compatible = "arm,cortex-a5";
61 next-level-cache = <&L2>;
63 enable-method = "amlogic,meson8b-smp";
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-exynos/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 # Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
25 select HAVE_ARM_SCU if SMP
34 select SRAM
58 Samsung Exynos3 (Cortex-A7) SoC based systems
68 Samsung Exynos4 (Cortex-A9) SoC based systems
74 Samsung Exynos5 (Cortex-A15/A7) SoC based systems
112 select EXYNOS_MCPM if SMP
|