1/* 2 * Copyright 2014 Carlo Caione <carlo@caione.org> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 * 22 * Or, alternatively, 23 * 24 * b) Permission is hereby granted, free of charge, to any person 25 * obtaining a copy of this software and associated documentation 26 * files (the "Software"), to deal in the Software without 27 * restriction, including without limitation the rights to use, 28 * copy, modify, merge, publish, distribute, sublicense, and/or 29 * sell copies of the Software, and to permit persons to whom the 30 * Software is furnished to do so, subject to the following 31 * conditions: 32 * 33 * The above copyright notice and this permission notice shall be 34 * included in all copies or substantial portions of the Software. 35 * 36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 43 * OTHER DEALINGS IN THE SOFTWARE. 44 */ 45 46#include <dt-bindings/clock/meson8b-clkc.h> 47#include <dt-bindings/gpio/meson8-gpio.h> 48#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> 49#include <dt-bindings/reset/amlogic,meson8b-reset.h> 50#include "meson.dtsi" 51 52/ { 53 model = "Amlogic Meson8 SoC"; 54 compatible = "amlogic,meson8"; 55 56 cpus { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 cpu0: cpu@200 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a9"; 63 next-level-cache = <&L2>; 64 reg = <0x200>; 65 enable-method = "amlogic,meson8-smp"; 66 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; 67 }; 68 69 cpu1: cpu@201 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a9"; 72 next-level-cache = <&L2>; 73 reg = <0x201>; 74 enable-method = "amlogic,meson8-smp"; 75 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; 76 }; 77 78 cpu2: cpu@202 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a9"; 81 next-level-cache = <&L2>; 82 reg = <0x202>; 83 enable-method = "amlogic,meson8-smp"; 84 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; 85 }; 86 87 cpu3: cpu@203 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a9"; 90 next-level-cache = <&L2>; 91 reg = <0x203>; 92 enable-method = "amlogic,meson8-smp"; 93 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; 94 }; 95 }; 96 97 pmu { 98 compatible = "arm,cortex-a9-pmu"; 99 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 103 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 104 }; 105 106 reserved-memory { 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges; 110 111 /* 2 MiB reserved for Hardware ROM Firmware? */ 112 hwrom@0 { 113 reg = <0x0 0x200000>; 114 no-map; 115 }; 116 117 /* 118 * 1 MiB reserved for the "ARM Power Firmware": this is ARM 119 * code which is responsible for system suspend. It loads a 120 * piece of ARC code ("arc_power" in the vendor u-boot tree) 121 * into SRAM, executes that and shuts down the (last) ARM core. 122 * The arc_power firmware then checks various wakeup sources 123 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or 124 * simply the power key) and re-starts the ARM core once it 125 * detects a wakeup request. 126 */ 127 power-firmware@4f00000 { 128 reg = <0x4f00000 0x100000>; 129 no-map; 130 }; 131 }; 132 133 scu@c4300000 { 134 compatible = "arm,cortex-a9-scu"; 135 reg = <0xc4300000 0x100>; 136 }; 137}; /* end of / */ 138 139&aobus { 140 pmu: pmu@e0 { 141 compatible = "amlogic,meson8-pmu", "syscon"; 142 reg = <0xe0 0x18>; 143 }; 144 145 pinctrl_aobus: pinctrl@84 { 146 compatible = "amlogic,meson8-aobus-pinctrl"; 147 reg = <0x84 0xc>; 148 #address-cells = <1>; 149 #size-cells = <1>; 150 ranges; 151 152 gpio_ao: ao-bank@14 { 153 reg = <0x14 0x4>, 154 <0x2c 0x4>, 155 <0x24 0x8>; 156 reg-names = "mux", "pull", "gpio"; 157 gpio-controller; 158 #gpio-cells = <2>; 159 gpio-ranges = <&pinctrl_aobus 0 0 16>; 160 }; 161 162 uart_ao_a_pins: uart_ao_a { 163 mux { 164 groups = "uart_tx_ao_a", "uart_rx_ao_a"; 165 function = "uart_ao"; 166 }; 167 }; 168 169 i2c_ao_pins: i2c_mst_ao { 170 mux { 171 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; 172 function = "i2c_mst_ao"; 173 }; 174 }; 175 176 ir_recv_pins: remote { 177 mux { 178 groups = "remote_input"; 179 function = "remote"; 180 }; 181 }; 182 183 pwm_f_ao_pins: pwm-f-ao { 184 mux { 185 groups = "pwm_f_ao"; 186 function = "pwm_f_ao"; 187 }; 188 }; 189 }; 190}; 191 192&cbus { 193 clkc: clock-controller@4000 { 194 #clock-cells = <1>; 195 #reset-cells = <1>; 196 compatible = "amlogic,meson8-clkc"; 197 reg = <0x8000 0x4>, <0x4000 0x400>; 198 }; 199 200 reset: reset-controller@4404 { 201 compatible = "amlogic,meson8b-reset"; 202 reg = <0x4404 0x9c>; 203 #reset-cells = <1>; 204 }; 205 206 analog_top: analog-top@81a8 { 207 compatible = "amlogic,meson8-analog-top", "syscon"; 208 reg = <0x81a8 0x14>; 209 }; 210 211 pwm_ef: pwm@86c0 { 212 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; 213 reg = <0x86c0 0x10>; 214 #pwm-cells = <3>; 215 status = "disabled"; 216 }; 217 218 pinctrl_cbus: pinctrl@9880 { 219 compatible = "amlogic,meson8-cbus-pinctrl"; 220 reg = <0x9880 0x10>; 221 #address-cells = <1>; 222 #size-cells = <1>; 223 ranges; 224 225 gpio: banks@80b0 { 226 reg = <0x80b0 0x28>, 227 <0x80e8 0x18>, 228 <0x8120 0x18>, 229 <0x8030 0x30>; 230 reg-names = "mux", "pull", "pull-enable", "gpio"; 231 gpio-controller; 232 #gpio-cells = <2>; 233 gpio-ranges = <&pinctrl_cbus 0 0 120>; 234 }; 235 236 sd_a_pins: sd-a { 237 mux { 238 groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", 239 "sd_d3_a", "sd_clk_a", "sd_cmd_a"; 240 function = "sd_a"; 241 }; 242 }; 243 244 sd_b_pins: sd-b { 245 mux { 246 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", 247 "sd_d3_b", "sd_clk_b", "sd_cmd_b"; 248 function = "sd_b"; 249 }; 250 }; 251 252 sd_c_pins: sd-c { 253 mux { 254 groups = "sd_d0_c", "sd_d1_c", "sd_d2_c", 255 "sd_d3_c", "sd_clk_c", "sd_cmd_c"; 256 function = "sd_c"; 257 }; 258 }; 259 260 spi_nor_pins: nor { 261 mux { 262 groups = "nor_d", "nor_q", "nor_c", "nor_cs"; 263 function = "nor"; 264 }; 265 }; 266 267 eth_pins: ethernet { 268 mux { 269 groups = "eth_tx_clk_50m", "eth_tx_en", 270 "eth_txd1", "eth_txd0", 271 "eth_rx_clk_in", "eth_rx_dv", 272 "eth_rxd1", "eth_rxd0", "eth_mdio", 273 "eth_mdc"; 274 function = "ethernet"; 275 }; 276 }; 277 278 pwm_e_pins: pwm-e { 279 mux { 280 groups = "pwm_e"; 281 function = "pwm_e"; 282 }; 283 }; 284 285 uart_a1_pins: uart-a1 { 286 mux { 287 groups = "uart_tx_a1", 288 "uart_rx_a1"; 289 function = "uart_a"; 290 }; 291 }; 292 293 uart_a1_cts_rts_pins: uart-a1-cts-rts { 294 mux { 295 groups = "uart_cts_a1", 296 "uart_rts_a1"; 297 function = "uart_a"; 298 }; 299 }; 300 }; 301}; 302 303&ahb_sram { 304 smp-sram@1ff80 { 305 compatible = "amlogic,meson8-smp-sram"; 306 reg = <0x1ff80 0x8>; 307 }; 308}; 309 310&efuse { 311 compatible = "amlogic,meson8-efuse"; 312 clocks = <&clkc CLKID_EFUSE>; 313 clock-names = "core"; 314}; 315 316ðmac { 317 clocks = <&clkc CLKID_ETH>; 318 clock-names = "stmmaceth"; 319}; 320 321&gpio_intc { 322 compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc"; 323 status = "okay"; 324}; 325 326&hwrng { 327 compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; 328 clocks = <&clkc CLKID_RNG0>; 329 clock-names = "core"; 330}; 331 332&i2c_AO { 333 clocks = <&clkc CLKID_CLK81>; 334}; 335 336&i2c_A { 337 clocks = <&clkc CLKID_CLK81>; 338}; 339 340&i2c_B { 341 clocks = <&clkc CLKID_CLK81>; 342}; 343 344&L2 { 345 arm,data-latency = <3 3 3>; 346 arm,tag-latency = <2 2 2>; 347 arm,filter-ranges = <0x100000 0xc0000000>; 348 prefetch-data = <1>; 349 prefetch-instr = <1>; 350 arm,shared-override; 351}; 352 353&pwm_ab { 354 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; 355}; 356 357&pwm_cd { 358 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; 359}; 360 361&saradc { 362 compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; 363 clocks = <&clkc CLKID_XTAL>, 364 <&clkc CLKID_SAR_ADC>; 365 clock-names = "clkin", "core"; 366}; 367 368&sdio { 369 compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; 370 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; 371 clock-names = "core", "clkin"; 372}; 373 374&spifc { 375 clocks = <&clkc CLKID_CLK81>; 376}; 377 378&uart_AO { 379 compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; 380 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>; 381 clock-names = "baud", "xtal", "pclk"; 382}; 383 384&uart_A { 385 compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; 386 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>; 387 clock-names = "baud", "xtal", "pclk"; 388}; 389 390&uart_B { 391 compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; 392 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>; 393 clock-names = "baud", "xtal", "pclk"; 394}; 395 396&uart_C { 397 compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; 398 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>; 399 clock-names = "baud", "xtal", "pclk"; 400}; 401 402&usb0 { 403 compatible = "amlogic,meson8-usb", "snps,dwc2"; 404 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; 405 clock-names = "otg"; 406}; 407 408&usb1 { 409 compatible = "amlogic,meson8-usb", "snps,dwc2"; 410 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 411 clock-names = "otg"; 412}; 413 414&usb0_phy { 415 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; 416 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; 417 clock-names = "usb_general", "usb"; 418 resets = <&reset RESET_USB_OTG>; 419}; 420 421&usb1_phy { 422 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; 423 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; 424 clock-names = "usb_general", "usb"; 425 resets = <&reset RESET_USB_OTG>; 426}; 427