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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: "mmc-controller.yaml#"
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/
Darasan,sdhci.txt7 [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
9 [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
12 - compatible: Compatibility string. One of:
13 - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
14 - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
15 - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
16 - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
17 For this device it is strongly suggested to include arasan,soc-ctl-syscon.
18 - reg: From mmc bindings: Register location and length.
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/reset/
Dhisilicon,hi3660-reset.txt7 The reset controller registers are part of the system-ctl block on
8 hi3660 SoC.
11 - compatible: should be
12 "hisilicon,hi3660-reset"
13 - hisi,rst-syscon: phandle of the reset's syscon.
14 - #reset-cells : Specifies the number of cells needed to encode a
18 register from the syscon register base
25 compatible = "hisilicon,hi3660-iomcu", "syscon";
30 compatible = "hisilicon,hi3660-reset";
31 hisi,rst-syscon = <&iomcu>;
[all …]
Dhisilicon,hi6220-reset.txt7 The reset controller registers are part of the system-ctl block on
8 hi6220 SoC.
11 - compatible: should be one of the following:
12 - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller.
13 - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller.
14 - reg: should be register base and length as documented in the
16 - #reset-cells: 1, see below
20 compatible = "hisilicon,hi6220-sysctrl", "syscon";
22 #clock-cells = <1>;
23 #reset-cells = <1>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/
Dhisilicon,hi6220-reset.txt7 The reset controller registers are part of the system-ctl block on
8 hi6220 SoC.
11 - compatible: should be one of the following:
12 - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller.
13 - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller.
14 - "hisilicon,hi6220-aoctrl", "syscon" : For ao reset controller.
15 - reg: should be register base and length as documented in the
17 - #reset-cells: 1, see below
21 compatible = "hisilicon,hi6220-sysctrl", "syscon";
23 #clock-cells = <1>;
[all …]
/kernel/linux/linux-4.19/drivers/mmc/host/
Dsdhci-of-arasan.c3 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
8 * Based on sdhci-of-esdhc.c
22 #include <linux/clk-provider.h>
23 #include <linux/mfd/syscon.h>
31 #include "sdhci-pltfm.h"
40 * On some SoCs the syscon area has a feature where the upper 16-bits of
41 * each 32-bit register act as a write mask for the lower 16-bits. This allows
49 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
51 * @reg: Offset within the syscon of the register containing this field
53 * @shift: Bit offset within @reg of this field (or -1 if not avail)
[all …]
/kernel/linux/linux-5.10/drivers/mmc/host/
Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
19 #include <linux/mfd/syscon.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-pltfm.h"
55 * On some SoCs the syscon area has a feature where the upper 16-bits of
56 * each 32-bit register act as a write mask for the lower 16-bits. This allows
64 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/intel/
Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/agilex-clock.h>
12 compatible = "intel,socfpga-agilex";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/altera/
Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dsocfpga_arria10.dtsi17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
21 #address-cells = <1>;
22 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "altr,socfpga-a10-smp";
30 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
36 compatible = "arm,cortex-a9";
[all …]
Dsocfpga.dtsi18 #include <dt-bindings/reset/altr,rst-mgr.h>
21 #address-cells = <1>;
22 #size-cells = <1>;
36 #address-cells = <1>;
37 #size-cells = <0>;
38 enable-method = "altr,socfpga-smp";
41 compatible = "arm,cortex-a9";
44 next-level-cache = <&L2>;
47 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
[all …]
Drk3036.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
16 interrupt-parent = <&gic>;
[all …]
Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/power/rk3288-power.h>
11 #include <dt-bindings/soc/rockchip,boot-mode.h>
[all …]
/kernel/linux/linux-4.19/drivers/mtd/nand/raw/atmel/
Dnand-controller.c5 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
22 * Derived from Das U-Boot source code
23 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
26 * Add Programmable Multibit ECC support for various AT91 SoC
29 * Add Nand Flash Controller support for SAMA5 SoC
41 * - atmel_nand_: all generic structures/functions
42 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
44 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
46 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
48 * - <soc>_nand_: all SoC specific structures/functions
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
[all …]
Drk3036.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
16 interrupt-parent = <&gic>;
[all …]
Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
[all …]
/kernel/linux/linux-5.10/drivers/mtd/nand/raw/atmel/
Dnand-controller.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
27 * Add Programmable Multibit ECC support for various AT91 SoC
30 * Add Nand Flash Controller support for SAMA5 SoC
38 * - atmel_nand_: all generic structures/functions
39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
[all …]
/kernel/linux/linux-5.10/drivers/soc/qcom/
Dcpr.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
24 #include <linux/mfd/syscon.h>
27 #include <linux/nvmem-consumer.h>
29 /* Register Offsets for RB-CPR and Bit Definitions */
125 #define FUSE_REVISION_UNKNOWN (-1)
254 return !drv->loop_disabled; in cpr_is_allowed()
259 writel_relaxed(value, drv->base + offset); in cpr_write()
264 return readl_relaxed(drv->base + offset); in cpr_read()
272 val = readl_relaxed(drv->base + offset); in cpr_masked_write()
[all …]
/kernel/linux/linux-5.10/sound/soc/codecs/
Dmsm8916-wcd-digital.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/mfd/syscon.h>
14 #include <sound/soc.h>
331 /* Digital Gain control -38.4 dB to +38.4 dB in 0.3 dB steps */
332 static const DECLARE_TLV_DB_SCALE(digital_gain, -3840, 30, 0);
334 /* Cutoff Freq for High Pass Filter at -3dB */
360 snd_soc_dapm_to_component(w->dapm); in msm8x16_wcd_codec_set_iir_gain()
365 if (w->shift == 0) in msm8x16_wcd_codec_set_iir_gain()
367 else if (w->shift == 1) in msm8x16_wcd_codec_set_iir_gain()
428 struct wcd_iir_filter_ctl *ctl = in msm8x16_wcd_get_iir_band_audio_mixer() local
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/rockchip/
Drk3399.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/rockchip/
Drk3399.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
[all …]
/kernel/linux/patches/linux-4.19/hi3516dv300_patch/
Dhi3516dv300.patch1 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
3 --- a/arch/arm/Kconfig
5 @@ -330,7 +330,7 @@ config ARCH_MULTIPLATFORM
9 - select AUTO_ZRELADDR
14 @@ -751,6 +751,8 @@ source "arch/arm/mach-highbank/Kconfig"
16 source "arch/arm/mach-hisi/Kconfig"
18 +source "arch/arm/mach-hibvt/Kconfig"
20 source "arch/arm/mach-imx/Kconfig"
22 source "arch/arm/mach-integrator/Kconfig"
23 diff --git a/arch/arm/Makefile b/arch/arm/Makefile
[all …]
/kernel/linux/patches/linux-5.10/hi3516dv300_patch/
Dhi3516dv300.patch1 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
3 --- a/arch/arm/Kconfig
5 @@ -322,7 +322,7 @@ config ARCH_MULTIPLATFORM
9 - select AUTO_ZRELADDR
14 @@ -650,6 +650,8 @@ source "arch/arm/mach-highbank/Kconfig"
16 source "arch/arm/mach-hisi/Kconfig"
18 +source "arch/arm/mach-hibvt/Kconfig"
20 source "arch/arm/mach-imx/Kconfig"
22 source "arch/arm/mach-integrator/Kconfig"
23 diff --git a/arch/arm/Makefile b/arch/arm/Makefile
[all …]