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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/mtd/
Ddenali-nand.txt1 * Denali NAND controller
4 - compatible : should be one of the following:
5 "altr,socfpga-denali-nand" - for Altera SOCFPGA
6 "socionext,uniphier-denali-nand-v5a" - for Socionext UniPhier (v5a)
7 "socionext,uniphier-denali-nand-v5b" - for Socionext UniPhier (v5b)
8 - reg : should contain registers location and length for data and reg.
9 - reg-names: Should contain the reg names "nand_data" and "denali_reg"
10 - interrupts : The interrupt number.
11 - clocks: should contain phandle of the controller core clock, the bus
13 - clock-names: should contain "nand", "nand_x", "ecc"
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Ddenali,nand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mtd/denali,nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Denali NAND controller
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - altr,socfpga-denali-nand
16 - socionext,uniphier-denali-nand-v5a
17 - socionext,uniphier-denali-nand-v5b
19 reg-names:
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/kernel/linux/linux-4.19/drivers/mtd/nand/raw/
Ddenali_dt.c2 * NAND Flash Controller Device Driver for DT
26 #include "denali.h"
29 struct denali_nand_info denali; member
67 .compatible = "altr,socfpga-denali-nand",
71 .compatible = "socionext,uniphier-denali-nand-v5a",
75 .compatible = "socionext,uniphier-denali-nand-v5b",
84 struct device *dev = &pdev->dev; in denali_dt_probe()
88 struct denali_nand_info *denali; in denali_dt_probe() local
93 return -ENOMEM; in denali_dt_probe()
94 denali = &dt->denali; in denali_dt_probe()
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/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Ddenali_dt.c1 // SPDX-License-Identifier: GPL-2.0
3 * NAND Flash Controller Device Driver for DT
20 #include "denali.h"
67 .compatible = "altr,socfpga-denali-nand",
71 .compatible = "socionext,uniphier-denali-nand-v5a",
75 .compatible = "socionext,uniphier-denali-nand-v5b",
82 static int denali_dt_chip_init(struct denali_controller *denali, in denali_dt_chip_init() argument
93 dchip = devm_kzalloc(denali->dev, struct_size(dchip, sels, nsels), in denali_dt_chip_init()
96 return -ENOMEM; in denali_dt_chip_init()
98 dchip->nsels = nsels; in denali_dt_chip_init()
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/intel/
Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/agilex-clock.h>
12 compatible = "intel,socfpga-agilex";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/altera/
Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
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Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
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/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dsocfpga_arria10.dtsi17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
21 #address-cells = <1>;
22 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "altr,socfpga-a10-smp";
30 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
36 compatible = "arm,cortex-a9";
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Dsocfpga.dtsi18 #include <dt-bindings/reset/altr,rst-mgr.h>
21 #address-cells = <1>;
22 #size-cells = <1>;
36 #address-cells = <1>;
37 #size-cells = <0>;
38 enable-method = "altr,socfpga-smp";
41 compatible = "arm,cortex-a9";
44 next-level-cache = <&L2>;
47 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
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/kernel/linux/linux-4.19/
DMAINTAINERS28 'diff -u' to make the patch easy to merge. Be prepared to get your
38 See Documentation/process/coding-style.rst for guidance here.
44 See Documentation/process/submitting-patches.rst for details.
55 include a Signed-off-by: line. The current version of this
57 Documentation/process/submitting-patches.rst.
68 that the bug would present a short-term risk to other users if it
84 W: Web-page with status/info
85 B: URI for where to file bugs. A web-page with detailed bug
109 N: [^a-z]tegra all files whose path contains the word tegra
137 -----------------------------------
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/kernel/linux/linux-5.10/
DMAINTAINERS9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
97 W: *Web-page* with status/info
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