1* Denali NAND controller 2 3Required properties: 4 - compatible : should be one of the following: 5 "altr,socfpga-denali-nand" - for Altera SOCFPGA 6 "socionext,uniphier-denali-nand-v5a" - for Socionext UniPhier (v5a) 7 "socionext,uniphier-denali-nand-v5b" - for Socionext UniPhier (v5b) 8 - reg : should contain registers location and length for data and reg. 9 - reg-names: Should contain the reg names "nand_data" and "denali_reg" 10 - interrupts : The interrupt number. 11 - clocks: should contain phandle of the controller core clock, the bus 12 interface clock, and the ECC circuit clock. 13 - clock-names: should contain "nand", "nand_x", "ecc" 14 15Optional properties: 16 - nand-ecc-step-size: see nand.txt for details. If present, the value must be 17 512 for "altr,socfpga-denali-nand" 18 1024 for "socionext,uniphier-denali-nand-v5a" 19 1024 for "socionext,uniphier-denali-nand-v5b" 20 - nand-ecc-strength: see nand.txt for details. Valid values are: 21 8, 15 for "altr,socfpga-denali-nand" 22 8, 16, 24 for "socionext,uniphier-denali-nand-v5a" 23 8, 16 for "socionext,uniphier-denali-nand-v5b" 24 - nand-ecc-maximize: see nand.txt for details 25 26The device tree may optionally contain sub-nodes describing partitions of the 27address space. See partition.txt for more detail. 28 29Examples: 30 31nand: nand@ff900000 { 32 #address-cells = <1>; 33 #size-cells = <1>; 34 compatible = "altr,socfpga-denali-nand"; 35 reg = <0xff900000 0x20>, <0xffb80000 0x1000>; 36 reg-names = "nand_data", "denali_reg"; 37 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; 38 clock-names = "nand", "nand_x", "ecc"; 39 interrupts = <0 144 4>; 40}; 41