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Searched +full:stm32f469 +full:- +full:qspi (Results 1 – 8 of 8) sorted by relevance

/kernel/linux/linux-4.19/Documentation/devicetree/bindings/mtd/
Dstm32-quadspi.txt4 - compatible: should be "st,stm32f469-qspi"
5 - reg: the first contains the register location and length.
7 - reg-names: should contain the reg names "qspi" "qspi_mm"
8 - interrupts: should contain the interrupt for the device
9 - clocks: the phandle of the clock needed by the QSPI controller
10 - A pinctrl must be defined to set pins in mode of operation for QSPI transfer
13 - resets: must contain the phandle to the reset controller.
16 properties. Also see jedec,spi-nor.txt.
19 - reg: chip-Select number (QSPI controller may connect 2 nor flashes)
20 - spi-max-frequency: max frequency of spi bus
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dst,stm32-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/st,stm32-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI) bindings
10 - Christophe Kerello <christophe.kerello@st.com>
11 - Patrice Chotard <patrice.chotard@st.com>
14 - $ref: "spi-controller.yaml#"
18 const: st,stm32f469-qspi
22 - description: registers
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/kernel/linux/linux-5.10/drivers/spi/
Dspi-stm32-qspi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
9 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi-mem.h>
91 #define STM32_AUTOSUSPEND_DELAY -1
94 struct stm32_qspi *qspi; member
128 struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id; in stm32_qspi_irq() local
131 sr = readl_relaxed(qspi->io_base + QSPI_SR); in stm32_qspi_irq()
135 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_irq()
137 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
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/kernel/linux/linux-4.19/drivers/mtd/spi-nor/
Dstm32-quadspi.c4 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
29 #include <linux/mtd/spi-nor.h>
124 #define FSIZE_VAL(size) (__fls(size) - 1)
135 struct stm32_qspi *qspi; member
174 static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi) in stm32_qspi_wait_cmd() argument
179 if (readl_relaxed(qspi->io_base + QUADSPI_SR) & SR_TCF) in stm32_qspi_wait_cmd()
182 reinit_completion(&qspi->cmd_completion); in stm32_qspi_wait_cmd()
183 cr = readl_relaxed(qspi->io_base + QUADSPI_CR); in stm32_qspi_wait_cmd()
184 writel_relaxed(cr | CR_TCIE, qspi->io_base + QUADSPI_CR); in stm32_qspi_wait_cmd()
186 if (!wait_for_completion_interruptible_timeout(&qspi->cmd_completion, in stm32_qspi_wait_cmd()
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/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dstm32mp157c.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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/kernel/linux/linux-5.10/drivers/clk/
Dclk-stm32f4.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Inspired by clk-asm9260.c .
8 #include <linux/clk-provider.h>
25 #include <dt-bindings/clock/stm32fx-clock.h>
42 #define NONE -1
168 { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
250 { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
326 { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
407 * The APBx dividers are power-of-two dividers and, if *not* running in 1:1
424 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_recalc_rate()
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/kernel/linux/linux-4.19/drivers/clk/
Dclk-stm32f4.c4 * Inspired by clk-asm9260.c .
19 #include <linux/clk-provider.h>
36 #include <dt-bindings/clock/stm32fx-clock.h>
53 #define NONE -1
179 { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
261 { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
335 * The APBx dividers are power-of-two dividers and, if *not* running in 1:1
352 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_recalc_rate()
364 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_round_rate()
404 return ERR_PTR(-ENOMEM); in clk_register_apb_mul()
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dstm32mp151.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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