| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | nand-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
19 The ECC strength and ECC step size properties define the user
21 they request the ECC engine to correct {strength} bit errors per
24 The interpretation of these parameters is implementation-defined, so
31 pattern: "^nand-controller(@.*)?"
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| D | gpmi-nand.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale General-Purpose Media Interface (GPMI) binding
10 - Han Xu <han.xu@nxp.com>
13 - $ref: "nand-controller.yaml"
17 flash chips. The device tree may optionally contain sub-nodes
24 - enum:
25 - fsl,imx23-gpmi-nand
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mtd/ |
| D | gpmi-nand.txt | 1 * Freescale General-Purpose Media Interface (GPMI)
7 - compatible : should be "fsl,<chip>-gpmi-nand", chip can be:
13 - reg : should contain registers location and length for gpmi and bch.
14 - reg-names: Should contain the reg names "gpmi-nand" and "bch"
15 - interrupts : BCH interrupt number.
16 - interrupt-names : Should be "bch".
17 - dmas: DMA specifier, consisting of a phandle to DMA controller node
19 Refer to dma.txt and fsl-mxs-dma.txt for details.
20 - dma-names: Must be "rx-tx".
21 - clocks : clocks phandle and clock specifier corresponding to each clock
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | l2c2x0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
35 - arm,l220-cache
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | imx6ull-myir-mys-6ulx-eval.dts | 1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include "imx6ull-myir-mys-6ulx.dtsi"
12 model = "MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND";
13 compatible = "myir,imx6ull-mys-6ulx-eval", "fsl,imx6ull";
17 fsl,use-minimum-ecc;
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| /kernel/linux/linux-4.19/drivers/mtd/nand/raw/ |
| D | mtk_nand.c | 5 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
18 #include <linux/dma-mapping.h>
94 #define MTK_NAME "mtk-nand"
151 struct mtk_ecc *ecc; member
188 return (u8 *)p + i * chip->ecc.size; in data_ptr()
200 if (i < mtk_nand->bad_mark.sec) in oob_ptr()
201 poi = chip->oob_poi + (i + 1) * mtk_nand->fdm.reg_size; in oob_ptr()
202 else if (i == mtk_nand->bad_mark.sec) in oob_ptr()
203 poi = chip->oob_poi; in oob_ptr()
205 poi = chip->oob_poi + i * mtk_nand->fdm.reg_size; in oob_ptr()
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| D | tegra_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
31 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
37 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
38 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
153 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
182 struct mtd_oob_region ecc; member
204 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
208 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
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| D | marvell_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
22 #include <linux/dma-mapping.h>
23 #include <linux/dma/pxa-dma.h>
24 #include <linux/platform_data/mtd-nand-pxa3xx.h>
104 #define NDSR_CMDD(cs) BIT(8 - cs)
108 /* NAND ECC control register */
163 * Marvell ECC engine works differently than the others, in order to limit the
166 * a particular layout mixing data/spare/ecc is defined, with a possible last
170 * @chunk: Desired ECC chunk size on which the layout applies
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| D | nand_base.c | 7 * http://www.linux-mtd.infradead.org/doc/nand.html
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
61 struct nand_ecc_ctrl *ecc = &chip->ecc; in nand_ooblayout_ecc_sp() local
64 return -ERANGE; in nand_ooblayout_ecc_sp()
67 oobregion->offset = 0; in nand_ooblayout_ecc_sp()
68 if (mtd->oobsize == 16) in nand_ooblayout_ecc_sp()
69 oobregion->length = 4; in nand_ooblayout_ecc_sp()
71 oobregion->length = 3; in nand_ooblayout_ecc_sp()
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| /kernel/linux/linux-4.19/include/linux/mtd/ |
| D | rawnand.h | 2 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
86 #define NAND_CMD_NONE -1
95 #define NAND_DATA_IFACE_CHECK_ONLY -1
117 * Constants for Hardware ECC
119 /* Reset Hardware ECC for read */
121 /* Reset Hardware ECC for write */
123 /* Enable Hardware ECC before syndrome is read back from flash */
128 * ecc.correct() returns -EBADMSG.
148 * Chip requires ready check on read (for auto-incremented sequential read).
179 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
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| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/ |
| D | mtk_nand.c | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
10 #include <linux/dma-mapping.h>
90 #define MTK_NAME "mtk-nand"
147 struct mtk_ecc *ecc; member
186 return (u8 *)p + i * chip->ecc.size; in data_ptr()
198 if (i < mtk_nand->bad_mark.sec) in oob_ptr()
199 poi = chip->oob_poi + (i + 1) * mtk_nand->fdm.reg_size; in oob_ptr()
200 else if (i == mtk_nand->bad_mark.sec) in oob_ptr()
201 poi = chip->oob_poi; in oob_ptr()
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| D | denali.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright © 2009-2010, Intel Corporation and its suppliers.
6 * Copyright (c) 2017-2019 Socionext Inc.
12 #include <linux/dma-mapping.h>
23 #define DENALI_NAND_NAME "denali-nand"
31 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
39 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
41 #define DENALI_INVALID_BANK -1
50 return container_of(chip->controller, struct denali_controller, in to_denali_controller()
55 * Direct Addressing - the slave address forms the control information (command
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| D | tegra_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
31 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
37 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
38 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
153 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
182 struct mtd_oob_region ecc; member
204 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
208 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
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| D | marvell_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
13 * The main visible difference is that NFCv1 only has Hamming ECC
14 * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
21 * or 4) and each chunk will have its own ECC "digest" of 6B at the
28 * +-------------------------------------------------------------+
29 * | Data 1 | ... | Data N | ECC 1 | ... | ECCN | Free OOB bytes |
30 * +-------------------------------------------------------------+
33 * ECC) sections and potentially an extra one to deal with
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| /kernel/linux/linux-5.10/drivers/mtd/nand/ |
| D | ecc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
11 * designed to fit most cases, including parallel NANDs and SPI-NANDs.
13 * There are three main situations where instantiating this ECC engine makes
15 * - external: The ECC engine is outside the NAND pipeline, typically this
16 * is a software ECC engine, or an hardware engine that is
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
20 * controllers. In the pipeline case, the ECC bytes are
23 * - ondie: The ECC engine is inside the NAND pipeline, on the chip's side.
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| /kernel/linux/linux-5.10/include/linux/mtd/ |
| D | rawnand.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
73 #define NAND_CMD_NONE -1
82 #define NAND_DATA_IFACE_CHECK_ONLY -1
85 * Constants for Hardware ECC
87 /* Reset Hardware ECC for read */
89 /* Reset Hardware ECC for write */
91 /* Enable Hardware ECC before syndrome is read back from flash */
96 * ecc.correct() returns -EBADMSG.
122 * Chip requires ready check on read (for auto-incremented sequential read).
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| /kernel/linux/linux-4.19/drivers/mtd/nand/raw/gpmi-nand/ |
| D | gpmi-nand.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
16 #include "gpmi-nand.h"
17 #include "bch-regs.h"
20 #define GPMI_NAND_GPMI_REGS_ADDR_RES_NAME "gpmi-nand"
34 * We may change the layout if we can get the ECC info from the datasheet,
35 * else we will use all the (page + OOB).
42 struct bch_geometry *geo = &this->bch_geometry; in gpmi_ooblayout_ecc()
45 return -ERANGE; in gpmi_ooblayout_ecc()
47 oobregion->offset = 0; in gpmi_ooblayout_ecc()
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| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/gpmi-nand/ |
| D | gpmi-nand.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
18 #include <linux/dma/mxs-dma.h>
19 #include "gpmi-nand.h"
20 #include "gpmi-regs.h"
21 #include "bch-regs.h"
24 #define GPMI_NAND_GPMI_REGS_ADDR_RES_NAME "gpmi-nand"
52 while ((readl(addr) & mask) && --timeout) in clear_poll_bit()
96 while ((!(readl(reset_addr) & MODULE_CLKGATE)) && --timeout) in gpmi_reset_block()
116 return -ETIMEDOUT; in gpmi_reset_block()
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| /kernel/linux/linux-5.10/arch/s390/include/uapi/asm/ |
| D | pkey.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
31 /* Minimum size of a key blob */
40 /* the newer ioctls use a pkey_key_type enum for type information */
50 /* the newer ioctls use a pkey_key_size enum for key size information */
58 /* some of the newer ioctls use these flags */
113 __u16 cardnr; /* in: card to use or FFFF for any */
124 __u16 cardnr; /* in: card to use or FFFF for any */
136 __u16 cardnr; /* in: card to use or FFFF for any */
230 * (return -1 with errno ENODEV). You may use the PKEY_APQNS4KT ioctl to
234 * generating CCA cipher keys you can use one or more of the PKEY_KEYGEN_*
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| /kernel/linux/linux-4.19/Documentation/admin-guide/ |
| D | ras.rst | 33 -------------
44 * Memory – add error correction logic (ECC) to detect and correct errors;
47 Self-Monitoring, Analysis and Reporting Technology (SMART).
55 ---------------
57 Most mechanisms used on modern systems use use technologies like Hamming
68 * **Correctable Error (CE)** - the error detection mechanism detected and
72 * **Uncorrected Error (UE)** - the amount of errors happened above the error
73 correction threshold, and the system was unable to auto-correct.
75 * **Fatal Error** - when an UE error happens on a critical component of the
79 * **Non-fatal Error** - when an UE error happens on an unused component,
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| /kernel/linux/linux-4.19/drivers/mtd/nand/raw/brcmnand/ |
| D | brcmnand.c | 2 * Copyright © 2010-2015 Broadcom Corporation
25 #include <linux/dma-mapping.h>
136 /* List of NAND hosts (one for each chip-select) */
142 /* in-memory cache of the FLASH_CACHE, used only for some commands */
148 const u8 *cs_offsets; /* within each chip-select */
157 /* for low-power standby/resume only */
175 /* use for low-power standby/resume only */
206 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
220 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
222 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */
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| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/brcmnand/ |
| D | brcmnand.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2010-2015 Broadcom Corporation
16 #include <linux/dma-mapping.h>
87 #define FLASH_DMA_MODE_STOP_ON_ERROR BIT(1) /* stop in Uncorr ECC error */
233 /* List of NAND hosts (one for each chip-select) */
236 /* EDU info, per-transaction */
254 /* in-memory cache of the FLASH_CACHE, used only for some commands */
260 const u8 *cs_offsets; /* within each chip-select */
270 /* for low-power standby/resume only */
290 /* use for low-power standby/resume only */
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| /kernel/linux/linux-5.10/Documentation/admin-guide/ |
| D | ras.rst | 33 -------------
44 * Memory – add error correction logic (ECC) to detect and correct errors;
47 Self-Monitoring, Analysis and Reporting Technology (SMART).
55 ---------------
57 Most mechanisms used on modern systems use technologies like Hamming
68 * **Correctable Error (CE)** - the error detection mechanism detected and
72 * **Uncorrected Error (UE)** - the amount of errors happened above the error
73 correction threshold, and the system was unable to auto-correct.
75 * **Fatal Error** - when an UE error happens on a critical component of the
79 * **Non-fatal Error** - when an UE error happens on an unused component,
[all …]
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| /kernel/linux/linux-5.10/drivers/crypto/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
34 Use VIA PadLock for AES algorithm.
39 called padlock-aes.
48 Use VIA PadLock for SHA1/SHA256 algorithms.
53 called padlock-sha.
61 Say 'Y' here to use the AMD Geode LX processor on-board AES
65 will be called geode-aes.
104 down the use of the available crypto hardware.
113 kernel or userspace applications may use these functions.
131 AES cipher algorithms for use with protected key.
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| /kernel/linux/linux-5.10/include/linux/ |
| D | edac.h | 6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
26 #define EDAC_OPSTATE_INVAL -1
60 * enum dev_type - describe the type of memory DRAM chips used at the stick
93 * enum hw_event_mc_err_type - type of the detected error
95 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
97 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
98 * can't be corrected by ECC, but it is not
101 * it for example, by re-trying the operation).
102 * @HW_EVENT_ERR_DEFERRED: Deferred Error - Indicates an uncorrectable
108 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
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