| /third_party/uboot/u-boot-2020.01/include/configs/km/ |
| D | km-mpc83xx.h | 12 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ macro
|
| /third_party/uboot/u-boot-2020.01/board/gdsys/mpc8308/ |
| D | sdram.c | 49 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
|
| /third_party/uboot/u-boot-2020.01/board/mpc8308_p1m/ |
| D | sdram.c | 42 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
|
| /third_party/uboot/u-boot-2020.01/board/freescale/mpc8308rdb/ |
| D | sdram.c | 46 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
|
| /third_party/uboot/u-boot-2020.01/board/freescale/mpc8315erdb/ |
| D | sdram.c | 63 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; in fixed_sdram()
|
| /third_party/uboot/u-boot-2020.01/include/configs/ |
| D | mpc8308_p1m.h | 43 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 macro
|
| D | caddy2.h | 55 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ macro
|
| D | vme8349.h | 55 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ macro
|
| D | MPC8308RDB.h | 40 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 macro
|
| D | sbc8349.h | 50 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ macro
|
| D | MPC8349EMDS.h | 56 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ macro
|
| D | MPC8349EMDS_SDRAM.h | 56 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ macro
|
| D | MPC8349ITX.h | 150 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ macro
|
| D | MPC8315ERDB.h | 38 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 macro
|
| D | MPC837XEMDS.h | 39 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 macro
|
| D | MPC837XERDB.h | 62 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 macro
|
| D | hrcon.h | 28 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 macro
|
| D | strider.h | 28 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 macro
|
| D | MPC8569MDS.h | 99 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 macro
|
| /third_party/uboot/u-boot-2020.01/board/freescale/mpc837xerdb/ |
| D | mpc837xerdb.c | 105 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; in fixed_sdram()
|
| /third_party/uboot/u-boot-2020.01/board/freescale/mpc8349itx/ |
| D | mpc8349itx.c | 70 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; in fixed_sdram()
|
| /third_party/uboot/u-boot-2020.01/arch/powerpc/cpu/mpc83xx/ |
| D | spd_sdram.c | 765 #ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */ in spd_sdram()
766 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; in spd_sdram()
|
| /third_party/uboot/u-boot-2020.01/board/freescale/mpc837xemds/ |
| D | mpc837xemds.c | 265 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; in fixed_sdram()
|
| /third_party/uboot/u-boot-2020.01/board/freescale/mpc8569mds/ |
| D | mpc8569mds.c | 251 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
|
| /third_party/uboot/u-boot-2020.01/scripts/ |
| D | config_whitelist.txt | 2236 CONFIG_SYS_DDR_SDRAM_CLK_CNTL
|