1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
5 *
6 * Authors: Nick.Spence@freescale.com
7 * Wilson.Lo@freescale.com
8 * scottwood@freescale.com
9 *
10 * This files is mostly identical to the original from
11 * board\freescale\mpc8315erdb\sdram.c
12 */
13
14 #ifndef CONFIG_MPC83XX_SDRAM
15
16 #include <common.h>
17 #include <mpc83xx.h>
18 #include <spd_sdram.h>
19
20 #include <asm/bitops.h>
21 #include <asm/io.h>
22
23 #include <asm/processor.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 /* Fixed sdram init -- doesn't use serial presence detect.
28 *
29 * This is useful for faster booting in configs where the RAM is unlikely
30 * to be changed, or for things like NAND booting where space is tight.
31 */
fixed_sdram(void)32 static long fixed_sdram(void)
33 {
34 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
35 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
36 u32 msize_log2 = __ilog2(msize);
37
38 out_be32(&im->sysconf.ddrlaw[0].bar,
39 CONFIG_SYS_SDRAM_BASE & 0xfffff000);
40 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
41 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
42
43 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
44 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
45
46 /* Currently we use only one CS, so disable the other bank. */
47 out_be32(&im->ddr.cs_config[1], 0);
48
49 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
50 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
51 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
52 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
53 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
54
55 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
56 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
57 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
58 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
59
60 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
61 sync();
62
63 /* enable DDR controller */
64 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
65 sync();
66
67 return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
68 }
69
dram_init(void)70 int dram_init(void)
71 {
72 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
73 u32 msize;
74
75 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
76 return -ENXIO;
77
78 /* DDR SDRAM */
79 msize = fixed_sdram();
80
81 /* return total bus SDRAM size(bytes) -- DDR */
82 gd->ram_size = msize;
83
84 return 0;
85 }
86
87 #endif /* !CONFIG_MPC83XX_SDRAM */
88